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8 - channel, 24 - bit , simultaneous sampling adc data sheet ad7771 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 2017 analog devices, inc. all rights reserved. technical support www.analog.com features 8 - c hannel , 24- bit simultaneous sampling adc single - ended or true differential inputs pga per channel (gains of 1, 2, 4, and 8) low dc input current 4 na ( differential )/ 8 na ( single - ended ) up to 128 ksps odr per channel programmable odrs and bandwidth src for coherent sampling sampling rate resolution up to 15.2 10 ?6 sps low latency sinc3 and sinc5 filter path s adjustable phase synchronization internal 2.5 v reference two power modes high resolution mode low power mode optimizes power dissipation and performance low resolution sar adc for system and chip diagnostic s power supply bipolar (1.65 v) or unipolar (3.3 v ) supplies digital i / o supply: 1.8 v to 3.6 v performance te mperature range: ? 40c to +105c functional temperature range: ? 40c to +125c performance combined ac and dc p erformance 1 0 7 db snr/ dynamic range at 32 ksps in high resolution mode ( sinc 5) ? 109 db thd 8 ppm of fsr inl 15 v offset error 0.1% fs gain error 10 ppm/c typ ical temperature coefficient applications power quality and measurement applications general - p urpose data acquisition e lectroencephalography (eeg ) industrial process control general description the ad7771 1 is an 8 - channel, simultaneous sampling analog - to - digital converter (adc) . e ight full - adcs are on - chip. the ad7771 provides an ultralow input current to allow direct sensor connection. each input channel has a programmable gain stage allowing gains of 1, 2, 4, and 8 to map lower amplitude sensor outputs into the full - scale adc input range, maximizing the dynamic range of the signal chain. the ad7771 accepts a v ref voltage from 1 v up to 3.6 v. the analog inputs accept unipolar (0 v to v ref ) or true bipo lar ( v ref /2 v) analog input signals with 3.3 v or 1.65 v analog supply voltages, respectively. the analog inputs can be configured to accept true differential or single - ended signals to match differen t sensor output configurations. each channel contains an adc modulator and a sinc3 /sinc5 , low latency digital filter. a sample rate converter (src) is provided to allow fine resolution control over the ad7771 output data rate (odr) . this control can be used in applications where the odr resolution is required to maintain coherency with 0.01 hz changes in the line frequency. the src is programmable through the serial port interface (spi). the ad7771 implements two different interfaces: a data output interface and spi control interface. the adc data output inter face is dedicated to trans - mitting the adc conversion results from the ad7771 to the processor. the spi write s to and read s from the ad7771 configuration registers and for the control and reading of data from the successive approximation register (sar) adc . the spi can also be configured to output the - conversion data. the ad7771 includes a 12 - bit sar adc. this adc can be used for ad7771 diagnostics without having to decommission one of the - adc channels dedicated to system measurement func - tions. with the use of an external multiplexer, which can be controlled through the three general - purpose input/output pins (gpios), and signal conditioning, the sar adc can validate the - adc measurements in applications where functional safety is requi red. in addition, the ad7771 sar adc includes an internal multiplexer to sense internal nodes. the ad7771 contains a 2.5 v reference and reference buffer. the reference has a typical temperature coefficient of 1 0 ppm/c. the ad7771 offers two modes of ope ration: high resolution mode and low power mode. high resolution mode provides a higher dynamic range while consuming 16.6 mw per channel; low power mode consumes only 5.25 mw per channel at a reduced dynamic range specification. the specified operating t emperature range is ?40c to +105c, although the device is operational up to +125c. note that throughout this data sheet, certain terms are used to refer to either the multifunction pin s or a range of pins. the multi function pins, such as dclk0/sdo, are referred to either by the entire pin name or by a single function of the pin, for example, dclk0, when only that function is relevant. in the case of ranges of pins, avssx refer s to the following pins: avss1a, avss1b, avss2a, avss2b, avss3, and avss4. 1 this product is protected by at least u . s . patent no. 9.432,043 .
ad7771* product page quick links last content update: 07/28/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad7770 / ad7771 / ad7779 evaluation board ? ad7771 evaluation board documentation application notes ? an-1388: coherent sampling for power quality measurements using the ad7779 24-bit simultaneous sampling sigma-delta adc ? an-1392: how to calculate offset errors and input impedance in adc converters with chopped amplifiers ? an-1393: translating system level protection and measurement requirements to adc specifications ? an-1405: diagnostic features on the ad7770 and ad7779 data sheet ? ad7771: 8-channel, 24-bit simultaneous sampling adcs data sheet user guides ? ug-884: evaluating the ad7770, ad7771, and ad7779 8- channel, 24-bit, simultaneous sampling, sigma-delta adcs with power scaling software and systems requirements ? ad7770/ad7771/ad7779 - no-os driver tools and simulations ? ad7770/ad7771/ad7779 filter model ? ad7771 crc calculator ? ad7770/ad7771/ad7779 ibis model reference materials press ? analog devices improves monitoring and protection of smart grid transmission and distribution equipment design resources ? ad7771 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7771 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad7771 data sheet rev. 0 | page 2 of 98 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 revision history ............................................................................... 3 functional block diagram .............................................................. 4 specifications ..................................................................................... 5 doutx timing characterististics ............................................. 9 spi timing characterististics ................................................... 10 synchronization pins and reset timing characteristics ...... 11 sar adc timing characterististics ....................................... 12 gpio src update timing characterististics ......................... 12 absolute maximum ratings .......................................................... 13 thermal resistance .................................................................... 13 esd cautio n ................................................................................ 13 pin configuration and function descriptions ........................... 14 typical performance characteristics ........................................... 17 terminology .................................................................................... 32 theory of operat ion ...................................................................... 34 analog inputs .............................................................................. 34 transfer function ....................................................................... 35 core signal chain ....................................................................... 36 capacitive pga ........................................................................... 36 internal refer ence and reference buffers ............................... 36 integrated ldos ......................................................................... 37 clocking and sampling .............................................................. 37 digital reset and synchronization pins .................................. 37 digital filtering ........................................................................... 38 shutdown mode .......................................................................... 38 controlling the ad7771 ............................................................ 39 pin control mode ....................................................................... 39 spi control .................................................................................. 42 digital spi .................................................................................... 44 rms noise and re solution ............................................................ 47 high resolution mode ............................................................... 47 low power mode ........................................................................ 48 diagnostics and monitoring ......................................................... 49 self diagnostics error ................................................................ 49 monito ring using the ad7771 sar adc (spi control mode) ........................................................................................... 50 - adc diagnostics (spi control mode) ............................ 52 - ? output data ............................................................................. 53 adc conversion output header and data ........................ 53 sample rate converter (src) (spi control mode) .............. 54 data output interface ................................................................ 56 calculating the crc checksum .............................................. 60 register summary .......................................................................... 61 register details ............................................................................... 65 channel 0 configuration register ........................................... 65 channel 1 configuration register ........................................... 65 channel 2 configuration register ........................................... 66 channel 3 configuration register ........................................... 66 channel 4 configuration register ........................................... 67 channel 5 configuration register ........................................... 67 channel 6 configuration re gister ........................................... 68 channel 7 configuration register ........................................... 68 disable clocks to adc channel register .............................. 69 channel 0 sync offset register ................................................ 69 channel 1 sync offset register ................................................ 69 channel 2 sync offset register ................................................ 69 channel 3 sync offset register ................................................ 70 channel 4 sync offset register ................................................ 70 channel 5 sync offset register ................................................ 70 channel 6 sync offset register ................................................ 70 channel 7 sync offset register ................................................ 70 general user configuration 1 register ................................... 71 general user configuration 2 register ................................... 72 general user configuration 3 register ................................... 73 data output format register ................................................... 73 main adc meter and reference mux control register ...... 74 global diagnostics mux register ............................................. 75 gpio configuration register ................................................... 75 gpio data register .................................................................... 76 buffer con figuration 1 register ............................................... 76 buffer configuration 2 register ............................................... 76 channel 0 offset upper byte register ..................................... 77 channel 0 offset middle byte register ................................... 77 channel 0 offset lower byte register ..................................... 77 channel 0 gain upper byte register ....................................... 77 channel 0 gain middle byte register ..................................... 77 channel 0 gain lower byte register ....................................... 78
data sheet ad7771 rev. 0 | page 3 of 98 channel 1 offset upper byte register ..................................... 78 channel 1 offset middle byte register .................................... 78 channel 1 offset lower byte register ..................................... 78 channel 1 gain upper byte register ........................................ 78 channel 1 gain middle byte register ...................................... 79 channel 1 gain lower byte register ........................................ 79 channel 2 offset upper byte register ..................................... 79 channel 2 offset middle byte register .................................... 79 channel 2 offset lower byte register ..................................... 79 channel 2 gain upper byte register ........................................ 80 channel 2 gain middle byte register ...................................... 8 0 channel 2 gain lower byte register ........................................ 80 channel 3 offset upper byte register ..................................... 80 channel 3 offset middle byte register .................................... 80 channel 3 offset lower byte register ..................................... 81 channel 3 gain upper byte register ........................................ 81 channel 3 gain middle byte register ...................................... 81 channel 3 gain lower byte register ........................................ 81 channel 4 offset upper byte register ..................................... 81 channel 4 offset middle byte register .................................... 82 channel 4 offset lower byte register ..................................... 82 channel 4 gain upper byte register ........................................ 82 channel 4 gain middle byte register ...................................... 82 channel 4 gain lower byte register ........................................ 82 channel 5 offset upper byte register ..................................... 83 channel 5 offset middle byte register .................................... 83 channel 5 offset lower byte register ..................................... 83 channel 5 gain upper byte register ........................................ 83 channel 5 gain middle byte register ...................................... 83 channel 5 gain lower byte register ........................................ 84 channel 6 offset upper byte register ..................................... 84 channel 6 offset middle byte register .................................... 84 channel 6 offset lower byte register ..................................... 84 channel 6 gain upper b yte register ........................................ 84 channel 6 gain middle byte register ...................................... 85 channel 6 gain lower byte register ....................................... 85 channel 7 offset upper byte register ..................................... 85 channel 7 offset middle byte register .................................... 85 channel 7 offset lower byte register ..................................... 85 channel 7 gain upper byte register ....................................... 86 channel 7 gain middle byte register ...................................... 86 channel 7 gain lower byte register ....................................... 86 channel 0 status register .......................................................... 86 channel 1 status register .......................................................... 87 channel 2 status register .......................................................... 87 channel 3 status register .......................................................... 88 channel 4 status register .......................................................... 88 channel 5 status register .......................................................... 89 ch annel 6 status register .......................................................... 89 channel 7 status register .......................................................... 90 channel 0/channel 1 dsp errors register .............................. 90 channel 2/channel 3 dsp errors register .............................. 91 channel 4/channel 5 dsp errors register .............................. 91 channel 6/channel 7 dsp errors register .............................. 92 channel 0 to channel 7 error register enable register ....... 92 general errors register 1 ........................................................... 93 general errors register 1 enable .............................................. 93 general errors register 2 ........................................................... 94 general errors register 2 enable .............................................. 94 error status register 1 ................................................................ 95 error status register 2 ................................................................ 95 error status register 3 ................................................................ 96 deci mation rate (n) msb register ......................................... 96 decimation rate (n) lsb register ........................................... 96 decimation rate (if) msb register ......................................... 96 decimation rate (if) lsb register .......................................... 97 src load source and load update register .......................... 97 outline dimensions ........................................................................ 98 ordering guide ........................................................................... 98 revision history 6 / 20 1 7 revision 0 : initial version
ad7771 data sheet rev. 0 | page 4 of 98 functional block dia gram avdd1x ref_out refx+ vcm avdd2x avssx avdd4 convst_sar iovdd aregxcap dregcap clock manager xtal1 xtal2/mclk sync_in sync_out start refxC dclk drdy dout3 dout2 dout1 dout0 format1 format0 mode3/alert mode2/gpio2 mode1/gpio1 mode0/gpio0 alert/cs dclk2/sclk dclk1/sdi dclk0/sdo reset - adc ain0+ ain0C 280mv p-p - adc references ext_ref int_ref ain1+ ain1C - adc references ain2+ ain2C - adc references ain3+ ain3C - adc references ain4+ ain4C - adc references ain5+ ain5C references ain6+ ain6C references diagnostic inputs ain7+ ain7C sinc3/ sinc5 src filter gain offset common- mode voltage analog ldo 2.5v ref sinc3/ sinc5 src filter gain offset sinc3/ sinc5 src filter gain offset sinc3/ sinc5 src filter gain offset sinc3/ sinc5 src filter gain offset sinc3/ sinc5 src filter gain offset sinc3/ sinc5 src filter gain offset sinc3/ sinc5 src filter gain offset - adc - adc auxain+ auxainC data output interface register map and logic control hardware mode configuration spi interface ad7771 sar adc digital ldo pga pga pga pga pga pga pga pga 13802-001 figure 1.
data sheet ad7771 rev. 0 | page 5 of 98 specifications avdd1x = 1.65 v, avssx 1 = ?1.65 v ( dual supply operation) , avdd1x = 3.3 v, av s s x = analog ground ( agnd ) ( single - supply operation) , av dd2 x ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, ref x+ /refx? = 2.5 v avs sx (internal/external ) , master clock ( mclk ) = 8192 khz for high resolution mode and 4096 khz for low power mode , odr = 128 ksps for high resolution mode and 32 ksps for low power mode ; all specifications at t min to t max , unless otherwise noted. table 1 . parameter test conditions / comment s min typ max unit analog inputs differential input voltage range v ref = (ref x + ? ref x ?) v ref /pga gain v single - ended input voltage range 0 to v ref / pga gain v ainx common - mode input range avssx + 0.10 (avdd1 x + avss x )/2 avdd1 x ? 0.10 v absolute ainx voltage limits avssx + 0.10 avdd 1 x ? 0.10 v dc input current differential h igh resolution mode 4 na low power mode 1 na single - ended high resolution mode 8 na low power mode 2 na input current drift 50 p a/c ac input capacitance 8 pf programmable gain amplifier ( pga ) gain settings (pga gain ) 1, 2, 4, or 8 bandwidth small signal high resolution mode 2 mhz low power mode 512 khz large signal high resolution mode see figure 39, figure 40, and figure 44 low power mode see figure 42, figure 43, and figure 47 reference internal initial accuracy ref_out, t a = 25c 2.495 2.5 2.505 v temperature coefficient 10 38 ppm/c reference load current , i l ?10 +10 ma dc power supply rejection line regulation 95 db load regulation , ?v out /?i l 100 v/ma voltage noise , e n p - p 0.1 hz to 10 hz 6.8 v rms voltage noise density , e n 1 khz, 2.5 v reference 273.5 nv/hz turn on settling time 100 nf 1.5 ms external input voltage v ref = (refx+ ? refx?) 1 2.5 avdd1x v buffer headroom avssx + 0.1 avdd1x ? 0.1 v refx? input voltage avssx avdd1x ? refx+ v average refx input current current per channel reference buffer disabled, high resolution mode 18 a/v reference buffer precharge mode (pre - q), high resolution mode 600 na/v reference buffer disabled, low power mode 4.5 a/v reference buffer pre - q, low power mode 100 na/v reference buffer enabled, high resolution mode 12 na/v reference buffer enabled, low power mode 5 na/v
ad7771 data sheet rev. 0 | page 6 of 98 parameter test conditions / comment s min typ max unit temperature range specified performance t min to t max ?40 +105 c functional 2 t min to t max ?40 +125 c temperature sensor accuracy 2 c digital filter response group delay see the src group delay section settling time see the settling time section pass band ?0.1 db see the src bandwidth section ?3 db see the src bandwidth section decimation rate sinc3 16 4095.99 sinc5 16 2048 clock source frequency high resolution mode 0.655 8.192 mhz low power mode 1.3 4.096 mhz duty cycle 45:55 50:50 55:45 % - adc speed and performance resolution 24 bits odr high resolution mode 128 ksps low power mode 32 ksps no missing codes sinc3, up to 24 ksps 24 bits sinc5 24 bits ac accuracy dynamic range shorted inputs, pga gain = 1 128 ksps high resolution mode (sinc5) 95 db 32 ksps high resolution mode (sinc5) 107 db 16 ksps high resolution mode (sinc3) 105.9 db 4 ksps high resolution mode (sinc3) 116 db 32 ksps low power mode (sinc5) 94.5 db 8 ksps low power mode (sinc5) 106.5 db 8 ksps low power mode (sinc3) 95.8 db 2 ksps low power mode (sinc3) 111.8 db total harmonic distortion (thd) ?0.5 dbfs, high resolution mode ?109 db ?0.5 dbfs, low power mode ?105 db signal - to - noise - and - distortion ratio (sinad) f in = 60 hz 106 db spurious - free dynamic range (sfdr) high resolution mode, 16 ksps, pga gain = 1 132 db intermodulation distortion (imd) f a = 50 hz, f b = 51 hz, high resolution mode ?125 db f a = 50 hz, f b = 51 hz, low power mode ?105 db dc power supply rejection avdd1x = 3.3 v ?90 db dc common - mode rejection ratio 80 db crosstalk ?120 db dc accuracy integral nonlinearity (inl) endpoint method high resolution pga gain = 1 8 15 ppm of fsr other pga gains 4 15 ppm of fsr
data sheet ad7771 rev. 0 | page 7 of 98 parameter test conditions / comment s min typ max unit low power pga gain = 1 9 17 ppm of fsr other pga gains 6 15 ppm of fsr offset error 15 90 v offset error drift 0.25 v/c over time ?2 v/1000 hours offset matching 25 v gain error 0.1 % fs gai n error dri ft vs. temperature pga gain = 1 0.75 ppm/c gain matching 0.1 % sar adc speed and performance resolution 12 bits analog input range avss4 + 0.1 avdd4 ? 0.1 v analog input common - mode range avss4 + 0.1 (avdd4 + avss4)/2 avdd4 ? 0.1 v analog input current 100 na throughput 256 ksps dc accuracy differential mode inl 1.5 lsb differential nonlinearity (dnl) no missing codes (12 - bit) ?0.99 1 lsb offset 1 lsb gain 12 lsb ac performance signal - to - noise ratio (snr) 1 khz 66 db thd 1 khz ?81 db vcm pin output (v cm ) (avdd1x + avssx)/2 v load current, i l 1 ma load regulation, ?v out /?i l 12 mv/ma short - circuit current 5 ma logic inputs input voltage high, v ih 0.7 iovdd v low, v il 0.4 v hysteresis 0.1 v input currents ?10 +10 a logic outputs 3 output voltage high, v oh iovdd 3 v, i source = 1 ma 0.8 iovdd v 2.3 v iovdd < 3 v, i source = 500 a 0.8 iovdd v iovdd < 2.3 v, i source = 200 a 0.8 iovdd v low, v ol iovdd 3 v, i sink = 2 ma 0.4 v 2.3 v iovdd < 3 v, i sink = 1 ma 0.4 v iovdd < 2.3 v, i sink = 100 a 0.4 v leakage current floating state ?10 +10 a output capacitance floating state 10 pf - adc data output coding twos complement sar adc data output coding binary
ad7771 data sheet rev. 0 | page 8 of 98 parameter test conditions / comment s min typ max unit power supplies all - channels enabled avdd1x ? avssx 3.0 3.6 v i avdd1x 4 , 5 reference buffer pre - q, vcm enabled, internal reference enabled high resolution mode 18.3 23.7 ma low power mode 5 6.4 ma reference buffer enabled, vcm enabled, internal reference enabled high resolution mode 20.5 26.7 ma low power mode 5.5 7.1 ma reference buffer disabled, vcm disabled, internal reference disabled high resolution mode 14.3 18.8 ma low power mode 3.9 5.1 ma avdd2x ? avssx 2.2 3.6 v i avdd2x high resolution mode 10.2 10.65 ma low power mode 3.8 4 ma avdd4 ? avssx 3 3.6 v i avdd4 sar enabled 1.7 2 ma sar disabled 1 10 a avssx ? dgnd ?1.8 0 v iovdd ? dgnd 1.8 3.6 v i iovdd high resolution mode (sinc5) 14.3 17 ma low power mode (sinc5) 4.6 5.5 ma high resolution mode (sinc3) 12.2 14.2 ma low power mode (sinc3) 2.2 4.9 ma power dissipation 6 internal buffers bypassed, internal reference disabled, internal oscillator disabled, sar disabled high resolution mode 128 ksps 133 153 mw low power mode 32 ksps 42 48.5 mw power - down all adcs disabled 530 w 1 avssx refers to the following pins: avss1a, a vss1b, avss2a, avss2b, avdd3, and avss4. this t e rm is used throughout the data sheet. 2 at temperatures higher than 105c, the device can be operated normally, though slight degradation on the max imum /min imum specifications is expected because the se specifications are only guarantee d up to 105c. see the typical performance characteristics section for plots showing the typical performance of the device at high temperature s . 3 the sdo pin and the doutx pin are configured in the default mode of strength. 4 avdd1x = 3.3 v, avssx = gnd = ground, iovdd = 1.8 v, cmos clock. 5 disabling either th e vcm pin o r the internal reference results in a 40 a typical current consumption reduction. 6 power dissipation is calculated using the maximum supply voltage, 3.6 v.
data sheet ad7771 rev. 0 | page 9 of 98 dout x timing characteristi stics avdd1x = 1.65 v, avssx 1 = ?1.65 v (dual supply operation), avdd1x = 3.3 v, avssx = agnd (single - supply operation) , avdd2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, refx+/refx? = 2.5 v internal/external, mclk = 8192 khz; all specifications at t min to t max , unless otherwise noted. table 2 . parameter description 2 test conditions /comments min typ max unit t 1 mclk frequency 50:50 0.655 8.192 mhz t 2 mclk low time 60 ns t 3 mclk high time 60 ns t 4 dclk high time mclk/2 121 ns t 5 dclk low time mclk/2 121 ns t 6 mclk falling edge to dclk rising edge 45 ns t 7 mclk falling edge to dclk falling edge 45 ns t 8 dclk rising edge to drdy rising edge 2 ns t 9 dclk rising edge to drdy falling edge 1 ns t 10 doutx setup time 20 ns t 11 doutx hold time 20 ns 1 avssx refers to the following pins: avss1a, avss1b, avss2a , avss2b , avss3 , and avss4 . this te rm is used throughout the data sheet. 2 all input signals are s peci fied wit h t r = t f = 1 n s/v (10% to 90% of io v dd ) and timed from a voltage level of (v il + v ih )/2. mclk dclk drdy lsb msb msb C 1 lsb + 1 lsb doutx t 2 t 4 t 5 t 6 t 7 t 10 t 11 t 8 t 9 t 1 t 3 13802-002 figure 2 . data interface timing diagram
ad7771 data sheet rev. 0 | page 10 of 98 spi timing character ististics avdd1x = 1.65 v, avssx 1 = ?1.65 v (dual supply operation), avdd1x = 3.3 v, avssx = agnd, avdd2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, refx+/refx? = 2.5 v (internal/external), mclk = 8192 khz; all specifications at t min to t max , unless otherwise noted. table 3 . parameter description 2 test conditions/comments min typ max unit t 12 sclk period 50:50 30 mhz t 13 sclk low time 7 ns t 14 sclk high time 7 ns t 15 sclk rising edge to cs falling edge 10 ns t 16 cs falling edge to sclk rising edge 10 ns t 17 sclk rising edge to cs rising edge 10 ns t 18 cs rising edge to sclk rising edge 10 ns t 19 minimum cs high time 10 ns t 20 sdi setup time 5 ns t 21 sdi hold time 5 ns t 22a cs falling edge to sdo enable (spi = mode 0) 30 ns t 22b sclk falling edge to sdo enable (spi = mode 1) 49 ns t 23 sdo setup time 10 ns t 24 sdo hold time 10 ns t 25 cs rising edge to sdo disable 30 ns 1 avssx refers to the following pins: avss1a, avss1b, avss2a , avss2b , avss3, and avss4 . this te rm is used throughout the data sheet. 2 all input signals are spec ified with t r = t f = 1 ns/v (10% to 90% of iovdd) and timed from a voltage level of (v il + v ih )/2. cs sclk msb msb C 1 lsb + 1 lsb sdi msb msb C 1 lsb + 1 lsb sdo t 15 t 16 t 13 t 14 t 20 t 22a t 21 t 24 t 23 t 22b t 12 t 19 t 17 t 18 t 25 13802-003 figure 3 . spi control interface timing diagram
data sheet ad7771 rev. 0 | page 11 of 98 synchronization pins and reset timing cha racteristics avdd1x = 1.65 v, avssx 1 = ?1.65 v (dual supply operation), avdd1x = 3.3 v, avssx = agnd, avdd2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, refx+/refx ? = 2.5 v (internal/external), mclk = 8192 khz; all specifications at t min to t max , unless otherwise noted. table 4 . parameter description 2 test conditions/comments min typ max unit t 26 start setup time 10 ns t 27 start hold time mclk ns t 28 mclk falling edge to sync_out falling edge mclk ns t 29 sync_in setup time 10 ns t 30 sync_in hold time mclk ns t init_ sync_in sync_in rising edge to first drdy 16 ksps, high resolution mode 145 s t init_ reset reset rising edge to first drdy 16 ksps, high resolution mode 225 s t 31 reset hold time 2 mclk ns t power_up start time t power_up is not shown in figure 4 2 ms 1 avssx refers to the following pins: avss1a, avss1b, avss2a , avss2b , avss3, and avss4 . this te rm is used throughout the data sheet. 2 all input sign als a re specified with t r = t f = 1 ns/v (10% to 90% of iovdd) and timed from a voltage level of (v il + v ih ) /2. mclk start sync_out sync_in drdy reset t 26 t 27 t 28 t 29 t init_sync_in t 31 t init_reset t 30 13802-004 figure 4. synchronization pins and reset control interface timing diagram
ad7771 data sheet rev. 0 | page 12 of 98 sar adc timing chara cterististics avdd1x = 1.65 v, avssx 1 = ?1.65 v (dual supply operation), avdd1x = 3.3 v, avssx = agnd, avdd2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, refx+/refx? = 2.5 v (internal/external), mclk = 8192 khz; all specifications at t min to t max , unless otherwise note d. table 5 . parameter description 2 min typ max unit t 32 conversion time 1 3.4 s t 33 acquisition time 3 500 ns t 34 delay time 50 ns t 35 throughput data rate 256 ksps 1 avssx refers to the following pins: avss1a, avss1b, avss2 a, avss2b, avss3 and avss4. this term is used throughout the data sheet. 2 all input s ignals are specifie d with t r = t f = 1 ns/v (10% to 90% of iovdd) and timed from a voltage le vel of (v il + v ih )/ 2. 3 direct mode enabled. if deglitch mode is enabled, add 1.5 /mclk as described in table 29. cs convst_sar t 33 t 32 t 35 t 34 13802-005 figure 5 . sar adc timing diagram gpio src update timi ng characterististic s avdd1x = 1.65 v, avssx 1 = ?1.65 v (dual supply operation), avdd1x = 3.3 v, avssx = agnd, avdd2 ? avssx = 2.2 v to 3.6 v; iovdd = 1.8 v to 3.6 v; dgnd = 0 v, refx+ /refx? = 2.5 v (internal/external), mclk = 8192 khz; all specifications t min to t max , unless otherwise noted. table 6 . parameter description 2 min typ max unit t 36 gpio2 setup time 10 ns t 37 gpio2 hold time h igh resolution mode mclk ns gpio2 hold time l ow power mode 2 mclk ns t 38 mclk rising edge to gpio1 rising edge time 20 ns t 39 gpio0 setup time 5 ns t 40 gpio0 hold time mclk ns 1 avssx refers to the following pins: avss1a, avss1b, avss2a , avss2b , avss3 and avss4 . this te rm is used throughout the data sheet. 2 all input signals are specified with t r = t f = 1 ns/v (1 0% to 90% of io v dd ) and timed from a voltage level of (v il + v ih )/ 2. mclk gpio2 gpio1 gpio0 t 3 6 t 3 7 t 3 8 t 3 9 t 40 13802-006 figure 6 . gpio s for src upd ate timing diagram
data sheet ad7771 rev. 0 | page 13 of 98 absolute maximum rat ings table 7 . parameter rating any supply pin to avssx ?0.3 v to +3.96 v avssx to dgnd ?1.98 v to +0.3 v a regxcap to avssx ?0.3 v to +1.98 v d regcap to dgnd ?0.3 v to +1.98 v iovdd to dgnd ?0.3 v to +3.96 v iovdd to avssx ?0.3 v to +5.94 v avdd 4 to avssx ?0.3 v to +3.96 v analog input voltage avssx ? 0.3 v to avdd1x + 0.3 v or 3.96 v (whichever is less) refx input voltage avssx ? 0.3 v to avdd1x + 0.3 v or 3.96 v (whichever is less) aux a in avssx ? 0.3 v to avdd4 + 0.1 v or 3.96 v (whichever is less) digital input voltage to dgnd dgnd ? 0.3 v to iovdd + 0.3 v or 3.96 v (whichever is less) digital output voltage to dgnd dgnd ? 0.3 v to iovdd + 0.3 v or 3.96 v (whichever is less) xtal1 to dgnd dgnd ? 0.3 v to d regcap + 0.3 v or 1.98 v (whichever is less) ainx, auxain, and digital input current 10 ma operating temperature range ?40c to +125c junction temperature, t j maximum 150c storage temperature range ?65c to +150c reflow soldering 260c esd 2 kv f ield induced charged device model (f icdm ) 500 v stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reli ability. thermal resistance thermal performance is directly linked to printed circuit board ( pcb ) design and operating environment. close attention to pcb thermal design is required. table 8 . thermal resistance package type ja j b jt jb unit cp -64-15 1 no thermal vias 30.43 n/a 2 0.13 6.59 c/w 49 thermal vias 22.62 3.17 0.09 3.19 c/w 1 thermal impedance simulated values are based on a jedec 2s2p thermal test board. see jedec jesd51. 2 n/a means not applicable. esd caution
ad7771 data sheet rev. 0 | page 14 of 98 pin configuration an d function descripti ons ad7771 top view (not to scale) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 convst_sar alert/cs dclk2/sclk dclk1/sdi dclk0/sdo dgnd dregcap iovdd dout3 dout2 dout1 dout0 dclk drdy xtal1 xtal2/mclk 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 auxainC auxain+ avdd4 avss4 avss2a areg1cap avdd2a vcm clk_sel format0 format1 avss3 avdd2b areg2cap avss2b ref_out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ain0C ain0+ ain1C ain1+ avss1a avdd1a ref1C ref1+ ain2C ain2+ ain3C ain3+ mode0/gpio0 mode1/gpio1 mode2/gpio2 mode3/alert notes 1. exposed pad. connect the exposed pad to avssx. ain4C ain4+ ain5C ain5+ avss1b avdd1b ref2C ref2+ ain6C ain6+ ain7C ain7+ reset sync_in sync_out start 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 13802-007 figure 7 . pin configuration table 9 . pin function description s pin no. mnemonic type direction description 1 ain0 ? analog input input analog input channel 0 , negative . 2 ain0+ analog input input analog input channel 0 , positive . 3 ain1? analog input input analog input channel 1 , negative . 4 ain1+ analog input input analog input channel 1 , positive . 5 avss1a supply supply n egative front - end analog supply for channel 0 to channel 3, typical at ?1.65 v (dual supply) and agnd (single supply). connect all the avssx pins to the same potential . 6 avdd1a supply supply positive front - end analog supply for channel 0 t o channel 3, typical at avssx + 3.3 v. connect t his pin to avdd1b. 7 ref1? reference input negative reference input 1 for channel 0 to channel 3, typical at avssx. connect all the refx? pins to the same potential . 8 ref1+ reference input p ositive reference input 1 for channel 0 to channel 3, typical at ref1? + 2.5 v . 9 ain2? analog input input analog input channel 2 , negative . 10 ain2+ analog input input analog input channel 2 , positive . 11 ain3? analog input input analog input channel 3 , negative . 12 ain3+ analog input input analog input channel 3 , positive . 13 mode0/gpio0 digital i/o i / o mode 0 input in pin control mode (mode0). s ee table 14 for more details . configurable general - purpose input/output 0 in spi control mode (gpio0). if not in use, connect this pin to dgnd or iovdd. 14 mode1/gpio1 digital i/o i/o mode 1 in put in pin control mode (mode1). see table 14 for more details. configurable general - purpose input/output 1 in spi control mode (gpio1). if not i n use, connect this pin to dgnd or iovdd. 15 mode2/gpio2 digital i/o i/o mode 2 input in pin control mode (mode2). see table 14 for more details. configurable general - purpose input/output 2 in spi control mode (gpio2). if not in use, connect this pin to dgnd or iovdd. 16 mode3/alert digital i/o i / o mode 3 in put in pin control mode (mode3). see table 14 for more details. alert output in spi control mode (alert) .
data sheet ad7771 rev. 0 | page 15 of 98 pin no. mnemonic type direction description 17 convst_sar digital input input - output interface selection pin in pin control mode. s ee table 13 for more details . this pin also functions as the start for the sar conversion in spi control mode. 18 alert/ cs digital input input alert output in pin control mode (alert). chip select in spi control mode ( cs ). 19 dclk2 / sclk digital input input d ata clock frequency selection pin 2 in pin control mode (dclk2). s ee table 15 for more details . spi clock in spi control mode (sclk). 20 dclk1 / sdi digital input input data clock frequency selection pin 1 in pin control mode (dclk1). s ee table 15 for more details . spi data input in spi control mode (sdi). connect this pin to dgnd if the device is configured in pin control mode with the spi as the data output interface. 21 dclk0 / sdo digital output output data clock frequency selection pin 0 in pin control mode (dclk0). s ee table 15 for more details . spi data output in spi control mode (sdo). 22 dgnd supply supply digital ground. 23 dregcap supply output digital low dropout ( ldo ) output . decouple this pin to dgnd with a 1 f cap acitor. 24 iovdd supply supply digital levels input/output and digital ldo (dldo) supply from 1.8 v to 3.6 v. iovdd must not be lower than dregcap. 25 dout3 digital output i / o data output pin 3. if the device is configured in daisy - chain mode, this pin acts as an input pin. s ee the daisy - chain mode section for more details. 26 dout2 digital output i / o data output pin 2. if the device is configured in daisy - chain mode, this pin acts as an input pin. see the daisy - chain mode section for more details. 27 dout1 digital output output data output pin 1 . 28 dout0 digital output output data output pin 0 . 29 dclk digital output output data output clock . 30 drdy digital output output data output ready pin. 31 xtal1 clock input crystal 1 input connection. if cmos is used as a clock source, tie this pin to dgnd. see table 12 for more details . 32 xtal2/mclk clock input crystal 2 input connection (xtal2). see table 12 for more details. cmos clock (mclk). see table 12 for more details. 33 start digital input input synchronization pulse . this pin internally synchronizes an external start asynchronous pulse with mclk. the synchronize signal is shift ed out by the sync_out pin. if not in use, t ie this pin to dgnd . see the phase adjustment se cti on and the digital reset and synchronization pins section for more details. 34 sync_out digital output input synchronization signal . this pin generates a synchronous pulse generated and driven by hardware (via the start pin) or by software (general_user_ config_2, bit 0 ). if this pin is in use, it must be wired to the sync_in pin. see the phase adjustment section and the digital reset and synchronization pins section for more details. 35 sync_in digital input input r eset for the internal digital block and synchronize for multiple devices . see the digital reset and synchronization pins section for more detail s. 36 reset digital input input asynchronous reset pin. this pin r esets all registers to their default value. it is recommen ded to generate a pulse on this pin after the device is powered up because a slow slew rate in the supplies may generate an incorrect initialization in the digital block. 37 ain7+ analog input input analog input channel 7 , positive . 38 ain7? analog input input analog input channel 7 , negative . 39 ain6+ analog input input analog input channel 6 , positive . 40 ain6? analog input input analog input channel 6 , negative . 41 ref2+ reference input positiv e reference input 2 for channel 4 to channel 7 , typical at ref2? + 2.5 v . 42 ref2? reference input negative reference input 2 for channel 4 to channel 7, typical at avssx. connect all the refx? pins to the same potential . 43 avdd1b supply supply positive front - end analog supply for channel 4 to channel 7. connect t his pin t o avdd1a .
ad7771 data sheet rev. 0 | page 16 of 98 pin no. mnemonic type direction description 44 avss1b supply supply negative front - end analog supply for channel 4 to channel 7, t ypical at ? 1.65 v (dual supply) or agnd (single supply). connect all the avssx pins to the same potential. 45 ain5+ analog input input analog input channel 5 , positive . 46 ain5? analog input input analog input channel 5 , negative . 47 ain4+ analog input input analog input channel 4 , positive . 48 ain4? analog input input analog input channel 4 , negative . 49 ref_out reference output 2.5 v reference output . connect a 100 nf capacitor on this pin if using the internal reference. 50 avss2b supply supply negative analog supply . connect all the avssx pins together. 51 areg2cap supply output analog ldo output 2 . decouple this pin to avss2 b with a 1 f cap acitor. 52 avdd2b supply supply positive analog supply. connect t his pin to avdd2a . 53 avss3 supply supply negative analog ground. connect all the avssx to the same potential. 54 format1 digital input input output data frame 1. s ee table 13 for more details . 55 format0 digital input input output data frame 0. s ee table 13 for more details . 56 clk_sel digital input input sel ect clock source. s ee table 12 f or more details . 57 vcm analog output output common - mode voltage output, typical at ( avdd1 x + avss x ) /2 . 58 avdd2a supply input analog supply from 2.2 v to 3.6 v. avss2x must not be lower than aregxcap . connect t his pin to avdd2b . 59 areg1cap supply output analog ldo output 1 . decouple this pin to avss x with a 1 f capacitor. 60 avss2 a supply input negative analog supply. connect all the avssx pins to the same potential. 61 avss4 supply supply neg ative sar analog supply and reference . connect all avssx pin s to the same potential. 62 avdd4 supply supply positive sar analog supply and reference source. 63 auxain+ analog input input positive sar analog input channel . 64 auxain? analog input input negative sar analog input channel . epad supply input exposed pad. connect the exposed pad to avssx .
data sheet ad7771 rev. 0 | page 17 of 98 typical performance characteristics 10 C10 C8 C6 C4 C2 0 2 4 6 8 inl (ppm) input voltage (v) C2.48 C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 t a = 25c gain = 1 differential input signal v ref = 2.5v v cm = (avdd1x + avssx) 2 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13802-008 fig ure 8 . inl vs. input voltage and channel at 64 ksps, high resolution mode 10 8 6 4 2 0 C2 C4 C6 C8 C10 C2.48 2.48 inl (ppm) input voltage (v) C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c differential v in gain v ref = 2.5v v cm = (avdd1x + avssx) 2 13802-009 figure 9. inl vs . in put voltage and pga gain at 64 ksps, high resolution mod e C3 C2 C1 0 1 2 3 10 8 6 4 2 0 C2 C4 C6 C8 C10 inl (ppm) input voltage (v) gain = 1 differential input signal v ref = 2.5v v cm = (avdd1x + avssx) 2 t a = C40c t a = +25c t a = +105c t a = +125c 13802-010 figure 10 . inl vs . input voltage and temperature at 64 ksps , high resolution mode 15 10 5 0 C5 C10 C15 inl (ppm) C2.48 2.48 input voltage (v) C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 t a = 25c gain = 1 differential input signal v ref = 2.5v v cm = (avdd1x + avssx) 2 13802-0 1 1 figure 11 . inl vs. input voltage and channel at 16 ksps, low power mode 10 C10 C8 C6 C4 C2 0 2 4 6 8 inl (ppm) input voltage (v) C2.48 C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c differential v in gain v ref = 2.5v v cm = (avdd1x + avssx) 2 13802-012 figure 12 . inl vs. input voltage and pga gain at 16 ksps , low power mode 10 5 C5 0 C10 C15 C3 C2 C1 0 1 2 3 inl (ppm) input voltage (v) t a = C40c t a = +25c t a = +105c t a = +125c gain = 1 differential input signal v ref = 2.5v v cm = (avdd1x + avssx) 2 13802-013 figure 13 . in l vs . input voltage and temperature at 16 ksps , low power m ode
ad7771 data sheet rev. 0 | page 18 of 98 20 C20 C10 5 15 0 C15 C5 10 C4 C2 0 2 C3 C1 1 3 4 inl (ppm) input voltage (v) t a = 25c gain = 1 differential input signal v cm = (avdd1x + avssx) 2 v ref = 1.0v v ref = 1.5v v ref = 2.0v v ref = 2.5v v ref = 3.0v v ref = 3.3v 13802-014 figure 14 . inl vs . input voltage and reference voltage (v ref ) at 64 ksps , high resolution mode 10 C10 C8 C6 C4 C2 0 2 4 6 8 inl (ppm) input voltage (v) C2.48 C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 2.48 t a = 25c gain = 1 differential v in gain v ref = 2.5v v cm = 1.95v v cm = 1.65v v cm = 1.35v 13802-015 figure 15 . inl vs . input voltage and v cm at 64 ksps, high resolution mode 8388326 adc code 1000 900 800 700 600 500 400 300 200 100 0 sample count 8388340 8388354 8388368 8388382 8388396 8388410 8388424 8388438 8388452 8388466 8388480 8388494 8388508 8388522 8388536 8388550 8388564 8388578 8388592 8388606 gain = 1 gain = 2 gain = 4 gain = 8 v ref = 2.5v v cm = (avdd1x + avssx) 2 t a = 25c 13802-016 figure 16 . noise histogram at 16 ksps, high resolution mode , s inc 3 filter enabled C4 C3 4 input voltage (v) 15 10 5 0 C5 C10 C15 inl (ppm) C2 C1 0 1 2 3 t a = 25c gain = 1 differential input signal v cm = (avdd1x + avssx) 2 v ref = 2.5v v ref = 1.0v v ref = 1.5v v ref = 2.0v v ref = 2.5v v ref = 3.0v v ref = 3.3v 13802-017 figure 17 . inl vs . input voltage and reference voltage (v ref ) at 16 ksps , low power mode 15 10 5 0 C5 C10 C15 inl (ppm) C2.48 2.48 input voltage (v) C2.12 C1.77 C1.41 C1.06 C0.70 C0.35 0 0.35 0.70 1.06 1.41 1.77 2.12 t a = 25c gain = 1 differential input signal v ref = 2.5v v cm = 1.95v v cm = 1.65v v cm = 1.35v 13802-018 figure 18 . inl vs . input voltage and v cm at 16 ksps, low power mode 8388300 8388604 adc code 1000 900 800 700 600 500 400 300 200 100 0 sample count gain = 1 gain = 2 gain = 4 gain = 8 v ref = 2.5v v cm = (avdd1x + avssx) 2 t a = 25c 8388316 8388332 8388348 8388364 8388380 8388396 8388412 8388428 8388444 8388460 8388476 8388492 8388508 8388524 8388540 8388556 8388572 8388588 13802-019 figure 19 . noi se histogram at 4 ksps, low power mode , sinc 3 filter enabled
data sheet ad7771 rev. 0 | page 19 of 98 300 250 200 150 100 50 0 sample count adc code 8387690 8387760 8387830 8387900 8387970 8388040 8388110 8388180 8388250 8388320 8388390 8388460 8388530 8388600 8388670 8388740 8388810 8388880 8388950 8389020 8389090 8389160 8389230 gain = 1 gain = 2 gain = 4 gain = 8 v ref = 2.5v v cm = (avdd1x + avssx) 2 t a = 25c 13802-020 figure 20 . noise histogram at 64 ksps, high resolution mode , sinc 5 filter enabled 12 0 125 noise (v rms) temperature (c) 2 4 6 8 10 C40 25 105 gain = 1 gain = 2 gain = 4 gain = 8 v ref = 2.5v v cm = (avdd1x + avssx) 2 13802-021 figure 21 . noise vs. temperature at 16 ksps , high resolution mode , s inc3 filter enabled 18 0 noise (v rms) 2 4 6 8 10 12 14 16 125 temperature (c) C40 25 105 gain = 1 gain = 2 gain = 4 gain = 8 v ref = 2.5v v cm = (avdd1x + avssx) 2 13802-022 figure 22 . noise vs. temperature at 64 ksps, high resolution mode , sinc 5 filter enabled 300 250 200 150 100 50 0 sample count adc code 8387466 gain = 1 gain = 2 gain = 4 gain = 8 v ref = 2.5v v cm = (avdd1x + avssx) 2 t a = 25c 8387554 8387642 8387730 8387818 8387906 8387994 8388082 8388170 8388258 8388346 8388434 8388522 8388610 8388698 8388786 8388874 8388962 8389050 8389138 13802-023 figure 23 . noise histogram at 16 ksps, low power mode , sinc 5 filter enabled 12 0 125 noise (v rms) temperature (c) 2 4 6 8 10 C40 25 105 gain = 1 gain = 2 gain = 4 gain = 8 v ref = 2.5v v cm = (avdd1x + avssx) 2 13802-024 figure 24 . noise vs. temperature at 4 ksps, low power mode, sinc3 filter enabled 20 0 noise (v rms) 2 4 6 8 10 12 14 16 18 125 temperature (c) C40 25 105 gain = 1 gain = 2 gain = 4 gain = 8 v ref = 2.5v v cm = (avdd1x + avssx) 2 13802-025 figure 25 . noise vs. temperature at 16 ksps, low power mode , sinc 5 filter enabled
ad7771 data sheet rev. 0 | page 20 of 98 1.6 0 8192000 noise (v rms) clock frequency (hz) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 1.0 1.1 1.2 1.3 1.4 1.5 gain = 1 gain = 2 gain = 4 gain = 8 7708400 7224800 6741200 6257600 5774000 5290400 4806800 4323200 3839600 3356000 2872400 2388800 1905200 1421600 938000 454400 13802-026 v ref = 2.5v v cm = (avdd1x + avssx) 2 t a = 25c decimation = 256 f igure 26 . noise vs. clock frequency, high resolution mode 160 0 140 noise (nv/hz) odr (sps) 20 40 60 80 100 120 1000 4000 8000 16000 gain = 1 gain = 2 gain = 4 gain = 8 13802-027 figure 27 . noise vs. odr, high resolution mode, sinc3 filter enabled 180 0 40 80 120 160 20 60 100 140 noise (nv/hz) odr (sps) 8000 128000 gain = 1 gain = 2 gain = 4 gain = 8 32000 64000 13802-028 figure 28 . noise vs. odr, high resolution mode, sinc5 filter enabled 1.80 0 4096000 225280 noise (v rms) clock frequency (hz) 2.00 4.00 6.00 8.00 1.00 1.20 1.40 1.60 4015360 3773440 3531520 3249280 3007360 2765440 2523520 2241280 1999360 1757440 1475200 1233280 991360 709120 467200 gain = 1 gain = 2 gain = 4 gain = 8 13802-029 v ref = 2.5v v cm = (avdd1x + avssx) 2 t a = 25c decimation = 256 700 0 noise (nv/hz) odr (sps) 500 8000 gain = 1 gain = 2 gain = 4 gain = 8 2000 4000 100 200 300 400 500 600 13802-030 figure 30 . noise vs. odr, low power mode, sinc3 filter enabled 400 0 noise (nv/hz) 50 100 150 200 250 300 350 odr (sps) 1000 32000 gain = 1 gain = 2 gain = 4 gain = 8 8000 16000 13802-031 figure 31 . noise vs. odr, low power mode, sinc5 filter enabled
data sheet ad7771 rev. 0 | page 21 of 98 10 C180 amplitude (db) frequency (hz) 0 278.320 555.664 846.680 1125.977 1393.555 1673.828 1954.102 2234.375 2501.953 2769.531 3037.109 3304.687 3572.266 3839.844 4107.422 4388.672 4664.063 4938.477 5211.914 5485.352 5759.766 6033.203 6307.617 6580.078 6851.563 7125.977 7399.414 7672.852 7947.266 C170 C160 C150 C140 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v v cm = (avdd1x + avssx) 2 input frequency = 50hz 13802-032 figure 32 . fft plot, high resolution mode at 16 ksps , input frequency (f in ) = 50 hz, sinc3 filter enabled 0 63000 frequency (hz) 10 C180 amplitude (db) C170 C160 C150 C140 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 gain = 1 gain = 2 gain = 4 gain = 8 2250 4500 6750 9000 11250 13500 15750 18000 20250 22500 24750 27000 29250 31500 33750 36000 38250 40500 42750 45000 47250 49500 51750 54000 56250 58500 60750 t a = 25c v ref = 2.5v v cm = (avdd1x + avssx) 2 odr = 128ksps input frequency = 50hz 13802-033 figure 33 . fft plot, high resolution mode at 128 ksps , input frequency (f in ) = 50 hz, sinc5 filter enabled 0 7861.33 frequency (hz) 10 C180 amplitude (db) C170 C160 C150 C140 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v v cm = (avdd1x + avssx) 2 input frequency = 1khz 341.80 683.59 1025.39 1367.19 1708.98 2050.78 2392.58 2734.38 3076.17 3417.97 3759.77 4101.56 4443.36 4785.16 5126.95 5468.75 5810.55 6152.34 6494.14 6835.94 7177.73 7519.53 13802-034 figure 34 . fft plot, high resolution mode at 16 ksps , input frequency (f in ) = 1 k hz, sinc3 filter en abled 0 1982.42 frequency (hz) 10 C180 amplitude (db) C170 C160 C150 C140 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v v cm = (avdd1x + avssx) 2 input frequency = 50hz 68.36 136.72 205.08 273.44 341.80 410.16 478.52 546.88 615.23 683.59 751.95 820.31 888.67 957.03 1025.39 1093.75 1162.11 1230.47 1298.83 1367.19 1435.55 1503.91 1572.27 1640.63 1708.98 1777.34 1845.70 1914.06 13802-035 figure 35 . fft plot, low power mode at 4 ksps , input frequency (f in ) = 50 hz, sinc3 filter enabled 0 15750.0 frequency (hz) 10 C180 amplitude (db) C170 C160 C150 C140 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v v cm = (avdd1x + avssx) 2 odr = 32ksps input frequency = 50hz 562.5 1125.0 1687.5 2250.0 2812.5 3375.0 3937.5 4500.0 5062.5 5625.0 6187.5 6750.0 7312.5 7875.0 8437.5 9000.0 9562.5 10125.0 10687.5 11250.0 11812.5 12375.0 12937.5 13500.0 14062.5 14625.0 15187.5 13802-036 figure 36 . fft plot, low power mode at 32 ksps , input frequency (f in ) = 50 hz, sinc5 filter enabled 0 frequency (hz) 10 C180 amplitude (db) C170 C160 C150 C140 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 gain = 1 gain = 2 gain = 4 gain = 8 74.22 148.44 222.66 296.88 371.09 445.31 519.53 593.75 667.97 742.19 816.41 890.63 964.84 1039.06 1113.28 1187.50 1261.72 1335.94 1410.16 1484.38 1558.59 1632.81 1707.03 1781.25 1855.47 1929.69 t a = 25c v ref = 2.5v v cm = (avdd1x + avssx) 2 input frequency = 1khz 13802-037 figure 37 . fft plot, low power mode at 4 ksps , input frequency (f in ) = 1 k hz, sinc3 filter enabled
ad7771 data sheet rev. 0 | page 22 of 98 0 62968.75 frequency (hz) 10 C180 amplitude (db) C170 C160 C150 C140 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 gain = 1 gain = 2 gain = 4 gain = 8 2421.88 4843.75 7265.63 9687.50 12109.38 14531.25 16953.13 19375.00 21796.88 24218.75 26640.63 29062.50 31484.38 33906.25 36328.13 38750.00 41171.88 43593.75 46015.63 48437.50 50859.38 53281.25 55703.13 58125.00 60546.88 t a = 25c v ref = 2.5v v cm = (avdd1x + avssx) 2 odr = 128ksps input frequency = 1khz 0 13802-038 figure 38 . fft plot, high resolution mode at 128 ksps , input frequency (f in ) = 1 k hz, sinc5 filter enabled C100 C105 C110 C115 C120 C125 C130 10.0 thd (db) input frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 89.2 168.4 247.6 326.8 406.0 485.2 564.4 643.6 722.8 802.0 881.2 970.3 2860.0 5340.0 7820.0 10300.0 13090.0 15570.0 18050.0 20530.0 23010.0 25490.0 27970.0 30450.0 t a = 25c gain = 1 v ref = 2.5v v cm = (avdd1x + avssx) 2 v in = C0.5dbfs 13802-039 figure 39 . thd vs. input frequency at 64 ksps, high resolution mode, sinc5 filter enabled C100 C135 10.0 3910.0 thd (db) input frequency (hz) C130 C125 C120 C115 C110 C105 89.2 168.4 247.6 326.8 406.0 485.2 564.4 643.6 722.8 802.0 881.2 970.3 1180.0 1450.0 1720.0 2050.0 2350.0 2590.0 2890.0 3130.0 3400.0 3670.0 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v v in = C0.5dbfs 13802-040 figure 40 . thd vs. input frequency at 16 ksps, high resolution mode, sinc3 filter enabled 10 C180 0 amplitude (db) frequency (hz) C170 C160 C150 C140 C130 C120 C110 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 593.75 1187.50 1781.25 2375.00 2968.75 3562.50 4156.25 4750.00 5343.75 5937.50 6531.25 7125.00 7718.75 8312.50 8906.25 9500.00 10093.75 10687.50 11281.25 11875.00 12468.75 13062.50 13656.25 14250.00 14843.75 15437.50 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v v cm = (avdd1x + avssx) 2 odr = 32ksps input frequency = 1khz 13802-041 figure 41 . fft plot, low power mode at 32 ksps , input frequency (f in ) = 1 k hz, sinc5 filter enabled C100 C125 thd (db) 10.0 input frequency (hz) gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v v in = C0.5dbfs C120 C115 C110 C105 89.2 168.4 247.6 326.8 406.0 514.9 604.0 703.0 792.1 881.2 960.4 1280.0 1840.0 2400.0 2960.0 3520.0 4080.0 4710.0 5270.0 5830.0 6460.0 7020.0 7580.0 13802-042 figure 42 . thd vs. input frequency at 16 ksps, low power mode, sinc5 filter enabled 10.0 C100 C135 thd (db) input frequency (hz) C130 C125 C120 C115 C110 C105 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v v in = C0.5dbfs 49.6 89.2 128.8 168.4 208.0 247.6 287.2 326.8 366.4 406.0 455.5 514.9 554.5 604.0 643.6 703.0 742.6 792.1 841.6 881.2 920.8 960.4 13802-043 figure 43 . thd vs. input frequency at 4 ksps, low power mode, sinc3 filter enabled
data sheet ad7771 rev. 0 | page 23 of 9 8 C100 C140 0.172 4.644 thd (db) input voltage (v) C135 C130 C125 C120 C115 C110 C105 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v input frequency = 50hz 0.344 0.516 0.688 0.860 1.032 1.204 1.376 1.548 1.720 1.892 2.064 2.236 2.408 2.580 2.752 2.924 3.096 3.268 3.440 3.612 3.784 3.956 4.128 4.300 4.472 13802-044 figure 44 . thd vs. input voltage at 64 ksps, high resolution mode C125 1.0 3.3 reference voltage (v) C90 C120 C105 C95 C110 C115 C100 thd (db) 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref input frequency = 50hz 13802-045 figure 45 . thd vs. reference voltage at 64 ksps, high resolution mode C100 C118 212600 thd (db) mclk frequency (hz) C116 C114 C112 C110 C108 C106 C104 C102 535000 857400 1179800 1502200 1824600 2147000 2469400 2791800 3114200 3436600 3759000 4081400 4403800 4726200 5048600 5371000 5693400 6015800 6338200 6660600 6983000 7305400 7627800 7950200 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v input frequency = 50hz 13802-046 figure 46 . thd vs. master clock frequency, high resolution mode C100 C140 0.172 4.644 thd (db) input voltage (v) C135 C130 C125 C120 C115 C110 C105 0.344 0.516 0.688 0.860 1.032 1.204 1.376 1.548 1.720 1.892 2.064 2.236 2.408 2.580 2.752 2.924 3.096 3.268 3.440 3.612 3.784 3.956 4.128 4.300 4.472 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v input frequency = 50hz 13802-047 figure 47 . thd vs. input voltage at 16 ksps, low power mode gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref input frequency = 50hz C125 1.0 3.3 reference voltage (v) C90 C120 C105 C95 C110 C115 C100 thd (db) 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 13802-048 figure 48 . thd vs. reference voltage at 16 ksps, low power mode C100 C105 C110 C115 C120 C125 thd (db) 104320 mclk frequency (hz) 265600 426880 588160 749440 910720 1072000 1233280 1394560 1555840 1717120 1878400 2039680 2200960 2362240 2523520 2684800 2846080 3007360 3168640 3329920 3491200 3652480 3813760 3975040 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v input frequency = 50hz 13802-049 figure 49 . thd vs . master clock frequency, low power mode
ad7771 data sheet rev. 0 | page 24 of 98 125 80 1000 16000 snr (db) odr (sps) 85 90 95 100 105 110 115 120 4000 8000 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v v in = 0dbf s 13802-050 figure 50 . snr vs. odr at 16 ksps, high resolution mode (avddx = 3.6 v, iovdd = 3.6 v) 115 80 8000 128000 snr (db) odr (sps) 85 90 95 100 105 110 32000 64000 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v v in = 0dbf s 13802-051 figure 51 . snr vs. odr at 64 ksps, high resolution mode (avddx = 3.6 v, iovdd = 3.6 v) 1 2 4 8 pga gain 108 96 100 98 102 104 106 dynamic range (db) t a = 25c odr = 16ksps 13802-052 figure 52 . dynamic range vs. pga gain at 16 ksps, high resolution mode 500 2000 4000 8000 odr (sps) 120 80 snr (db) gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v v in = 0dbf s 85 90 95 100 105 110 115 13802-053 figure 53 . snr vs. odr at 4 ksps, low power mode (avddx = 3.6 v, iovdd = 3.6 v) 1000 8000 16000 32000 snr (db) odr (sps) 120 80 85 90 95 100 105 110 115 t a = 25c v ref = 2.5v v in = 0dbf s gain = 1 gain = 2 gain = 4 gain = 8 13802-054 figure 54 . snr vs. odr at 16 ksps, low power mode (avddx = 3.6 v, iovdd = 3.6 v) 108 94 1 2 4 8 dynamic range (db) pga gain t a = 25c odr = 4ksps 98 100 102 104 106 13802-055 figure 55 . dynamic range vs. pga gain at 4 ksps, low power mode
data sheet ad7771 rev. 0 | page 25 of 98 104 82 dynamic range (db) 1 2 4 8 pga gain t a = 25c odr = 64ksps 84 86 88 90 92 94 96 98 100 102 13802-056 figure 56 . dynamic range vs. pga gain at 64 ksps, high resolution mode 0 C40 1 8 offset error (v) t a = 25c v ref = 2.5v v in = 0v supply = avdd1x = 3.3v C35 C30 C25 C20 C15 C10 C5 2 4 pga gain ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13802-057 figure 57 . offset error vs. pga gain at 64 ksps, high resolution mode 0 C25 C20 C15 C10 C5 3.0 3.3 3.6 offset error (v) avdd1x supply gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v v in = 0v 13802-058 figure 58 . offset error vs. avdd1x supply, high resolution mode 105 80 dynamic range (db) t a = 25c odr = 16ksps 85 90 95 100 1 2 4 8 pga gain 13802-059 figure 59 . dynamic range vs. pga gain at 16 ksps, low power mode 0 C35 C30 C25 C15 C5 C20 10 offset error (v) t a = 25c v ref = 2.5v v in = 0v supply = avdd1x = 3.3v ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 1 8 2 4 pga gain 13802-060 figure 60 . offset error vs. pga gain at 16 ksps, low power mode 3.0 3.3 3.6 avdd1x supply gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c v ref = 2.5v v in = 0v 0 C25 C20 C15 C10 C5 offset error (v) 13802-061 figure 61 . offset erro r vs. avdd1x supply, low power mode
ad7771 data sheet rev. 0 | page 26 of 98 C50 40 30 20 10 0 C10 C20 C30 C40 C40 C20 0 20 40 60 80 100 120 offset drift (v) temperature (c) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 avdd1x = 3.3v 13802-062 figure 62 . offset drift vs. temperature C0.043 C0.035 C0.026 C0.017 C0.008 0 0.008 0.017 3.0 3.3 3.6 gain error (%) avdd1x supply (v) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 temperature = 25c gain = 1 v ref = 2.5v v in = 0dbfs 13802-063 figure 63 . gain error vs. avdd1x supply , high resolution mode C40 25 105 125 gain error (%) temperature (c) avdd1x = 3.3v v ref = 2.5v v in = 0dbfs C0.400 C0.035 C0.029 C0.023 C0.017 C0.011 C0.005 0 0.005 0.011 0.017 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13802-064 figure 64 . gain error vs. temperature, high resolution mode C20 C15 C10 C5 0 5 10 15 20 25 30 45 40 35 0 500 168 1000 gain error drift (ppm) time (hours) 13802-065 figure 65 . gain error drift vs. time 3.0 3.3 3.6 avdd1x supply (v) temperature = 25c gain = 1 v ref = 2.5v v in = 0dbfs gain error (%) C0.043 C0.035 C0.026 C0.017 C0.008 0 0.008 0.017 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13802-066 figure 66 . gain error vs. avdd1x supply , low power mode C0.400 C0.035 C0.029 C0.023 C0.017 C0.011 C0.005 0 0.005 0.011 0.017 C40 25 105 125 gain error (%) temperature (c) avdd1x = 3.3v v ref = 2.5v v in = 0dbfs ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13802-067 figure 67 . gain error vs. temperature, low power mode
data sheet ad7771 rev. 0 | page 27 of 98 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 1 2 4 8 gain error (%) pga gain high resolution low power temperature = 25c avdd1x = 3.3v v ref = 2.5v v in = 0dbfs 13802-068 figure 68 . channel gain mismatch 0.008 C0.010 C40 125 tue as % of input temperature (c) C0.008 C0.006 C0.004 C0.002 0 0.002 0.004 0.006 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 C30 C20 C10 0 10 20 30 40 50 60 70 80 90 100 110 v ref = 2.5v v in = C0.5dbfs supply = avdd1x = 3.3v 13802-069 figure 69 . total unadusted error (tue) (as percent of input ) vs. temperature, high resolution mode 3 C5 C3 0 2 C1 C4 C2 1 C2.5 C1.5 C0.5 0.5 1.5 C2.0 C1.0 0 1.0 2.0 2.5 input current (na) differential input voltage ((ainx+) C (ainxC)) v ref = 2.5v supply = avdd1x = 3.3v ainx+, v cm = 1.95v ainxC, v cm = 1.95v ainx+; v cm = 1.35v ainxC, v cm = 1.35v 13802-070 figure 70 . input current vs. differential input voltage , high resolution mode C40 25 105 125 reference voltage drift (mv) temperature (c) C6 4 3 2 1 0 C1 C2 C3 C4 C5 13802-071 fig ure 71 . internal reference voltage drift 0.006 C0.008 tue as % of input C0.006 C0.004 C0.002 0 0.002 0.004 C40 125 temperature (c) ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 C30 C20 C10 0 10 20 30 40 50 60 70 80 90 100 110 v ref = 2.5v v in = C0.5dbfs supply = avdd1x = 3.3v 13802-072 figure 72 . to tal unadusted error (tue) (as percent of input ) vs. temperature , low power mode 1.0 0.8 C0.8 C0.6 0 0.4 0.6 C0.2 C0.4 0.2 input current (na) C2.5 C1.5 C0.5 0.5 1.5 C2.0 C1.0 0 1.0 2.0 2.5 differential input voltage ((ainx+) C (ainxC)) v ref = 2.5v supply = avdd1x = 3.3v ainx+, v cm = 1.95v ainxC, v cm = 1.95v ainx+; v cm = 1.35v ainxC, v cm = 1.35v 13802-073 figure 73 . input current vs. differential input voltage , low power mode
ad7771 data sheet rev. 0 | page 28 of 98 10 5 0 C5 C10 C15 absolute input current (na) C60 C40 140 120 temperature (c) C20 0 20 40 60 80 100 ain0+ ain0C ain2+ ain2C v ref = 2.5v v in = 2.5v supply = avdd1x = 3.3v 13802-074 figure 74 . absolute input current vs. temperature, high resolution mode 4 C4 C2 1 3 0 C3 C1 2 differential input current (na) C2.5 C1.5 C0.5 0.5 1.5 C2.0 C1.0 0 1.0 2.0 2.5 differential input voltage ((ainx+) C (ainxC)) v ref = 2.5v supply = avdd1x = 3.3v ainx+ C ainxC, v cm = 1.95v ainx+ C ainxC, v cm = 1.35v 13802-075 figure 75 . differential input current vs. differential input voltage , high resolution mode 14 12 10 8 6 4 2 0 C60 140 differential input current (na) temperature (c) C40 C20 0 20 40 60 80 100 120 v ref = 2.5v v in = 2.5v supply = avdd1x = 3.3v 13802-076 figure 76 . differential input current vs. temperature, high resolution mode 6 4 2 0 C2 C4 C6 C8 absolute input current (na) C60 C40 140 120 temperature (c) C20 0 20 40 60 80 100 v ref = 2.5v v in = 2.5v supply = avdd1x = 3.3v ain0+ ain0C ain2+ ain2C 13802-077 figure 77 . absolute input current vs. temperature, low power mode 1.0 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1.0 v ref = 2.5v supply = avdd1x = 3.3v ainx+ C ainxC, v cm = 1.95v ainx+ C ainxC, v cm = 1.35v differential input current (na) differential input voltage ((ainx+) C (ainxC)) C2.5 C1.5 C0.5 0.5 1.5 C2.0 C1.0 0 1.0 2.0 2.5 13802-078 figure 78 . differential input current vs. differential input voltage , low power mode 12 10 8 6 4 2 0 C40 140 120 temperature (c) differential input current (na) C20 0 20 40 60 80 100 v ref = 2.5v v in = 2.5v supply = avdd1x = 3.3v 13802-079 figure 79 . differential input current vs. temperature, low power mode
data sheet ad7771 rev. 0 | page 29 of 98 0 ?140 250.608317 cmrr (db) input frequency (hz) ?120 ?100 ?80 ?60 ?40 ?20 11022.185 21793.762 32961.353 43732.93 54504.507 65751.301 76522.878 87294.455 98620.451 109392.029 120163.606 131331.196 142102.773 152874.35 164041.941 174813.518 185585.095 196752.686 gain = 1 gain = 2 gain = 4 gain = 8 v cm = 1.65v + 100mv p-p supply = avdd1x = 3.3v + 100mv p-p 13802-080 figure 80. cmrr vs. input frequency at 128 ksps, high resolution mode 0 ?160 20014.97 ac psr (db) input frequency(hz) ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 460014.31 880013.68 1340013.00 1740012.00 2220012.00 2640011.00 3040010.00 3480010.00 3900009.00 4520008.00 4920008.00 5360007.00 5780006.00 6200006.00 6620005.00 7020004.00 7440004.00 7860003.00 8360002.00 8780002.00 9200001.00 9620001.00 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c supply = avdd1x = 3.3v+100mvpp 13802-081 figure 81. ac psrr vs. input freque ncy at 128 ksps, high resolution mode 10 ?120 attenuation (db) 25 frequency (hz) ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 5144 10263 15382 20501 25620 30739 35858 40977 46096 51215 56334 61453 66572 71691 76810 81929 87048 92167 97286 102405 107524 112643 117762 122881 gain = 1 gain = 2 gain = 4 gain = 8 13802-082 figure 82. filter profiles at 64 ksps, high resolution mode 0 ?140 171.09249 cmrr (db) input frequency (hz) ?120 ?100 ?80 ?60 ?40 ?20 gain = 1 gain = 2 gain = 4 gain = 8 v cm = 1.65v + 100mv p-p supply = avdd1x = 3.3v + 100mv p-p 10921.382 21829.764 32738.145 43804.62 54554.909 65463.291 76371.673 87438.147 98346.529 109096.818 120163.292 130913.582 141821.964 152572.253 163638.727 174389.017 185139.306 195889.595 13802-083 figure 83. cmrr vs. input frequency at 32 ksps, low power mode 15.0 0 ?160 ac psr (db) input frequency(hz) ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 gain = 1 gain = 2 gain = 4 gain = 8 t a = 25c supply = avdd1x = 3.3v + 100mv p-p 400014.4 800013.8 1260013.0 1680012.0 2200012.0 2660011.0 3140010.0 3600010.0 4060009.0 4520008.0 4980008.0 5420007.0 5880006.0 6340005.0 6800005.0 7260004.0 7720003.0 8180003.0 8620002.0 9080001.0 9540001.0 13802-084 figure 84. ac psrr vs. input frequency at 32 ksps, low power mode 25 frequency (hz) 0 ?120 attenuation (db) gain = 1 gain = 2 gain = 4 gain = 8 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 1304 2583 3862 5141 6420 7699 8978 10257 11536 12815 14094 15373 16652 17931 19210 20489 21768 23047 24326 25605 26884 28163 29442 30721 13802-085 figure 85. filter profiles at 16 ksps, low power mode
ad7771 data sheet rev. 0 | page 30 of 98 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 supply voltage (v) 20 18 16 14 12 10 8 6 4 2 0 supply current (ma) avdd1x avdd2x avdd4 iovdd 13802-086 figure 86 . supply current vs. supply voltage, high resolution mode 30 25 20 15 10 5 0 C40 supply current (ma) avdd1x avdd2x avdd4 iovdd 120 temperature (c) C20 0 20 40 60 80 100 13802-087 figure 87 . supply current vs. temperature high resolution mode C800 C600 C400 C200 0 200 400 600 800 C35.263 C29.594 C22.185 C15.223 C7.366 C0.405 7.006 14.429 22.067 29.170 36.646 44.122 52.009 58.557 66.064 74.427 81.446 89.252 96.238 105.348 112.092 119.542 123.075 reference input current (na) temperature (c) ref1C ref1+ ref2C ref2+ 13802-088 figure 88 . reference input current vs. temperature, high resolution mode 6 5 4 3 2 1 0 supply current (ma) 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 supply voltage (v) avdd1x avdd2x avdd4 iovdd 13802-089 figure 89 . supply current vs. supply voltage, low power mode 7 6 5 4 3 2 1 0 C40 120 supply current (ma) temperature (c) C20 0 20 40 60 80 100 avdd1x avdd2x avdd4 iovdd 13802-090 figure 90 . supply current vs. temperature low power mode C35.263 C29.594 C22.185 C15.223 C7.366 C0.405 7.006 14.429 22.067 29.170 36.646 44.122 52.009 58.557 66.064 74.427 81.446 89.252 96.238 105.348 112.092 119.542 123.075 reference input current (na) temperature (c) C600 C500 C400 C300 C200 C100 0 100 200 300 ref1C ref1+ ref2C ref2+ 13802-091 figure 91 . reference input current vs. temperature, low power mode
data sheet ad7771 rev. 0 | page 31 of 98 0 80 70 60 50 40 30 20 10 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 shutdown supply current (a) supply voltage (v) avdd1x avdd2x avdd4 iovdd 13802-092 figure 92 . shutdown supply current vs. supply voltage 60 50 40 30 20 10 0 power consumption (mw) 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 supply voltage (v) avdd1x avdd2x avdd4 iovdd 13802-093 figure 93 . power consumption per channel vs. supply voltage , high resolution mode 90 80 70 50 60 30 40 10 20 0 power dissipation (mw) C40 120 temperature (c) C20 0 20 40 60 80 100 avdd1x avdd2x avdd4 iovdd 13802-094 figure 94 . power dissipation vs. temperature, high resolution mode 0 500 400 300 200 100 450 350 250 150 50 C60 C40 C20 0 20 40 60 80 100 140 120 shutdown supply current (a) temperature (c) avdd1x avdd2x avdd4 iovdd 13802-095 figure 95 . shutdown supply current vs. temperature 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 supply voltage (v) 20 18 16 14 12 10 8 6 4 2 0 power consumption (mw) avdd1x avdd2x avdd4 iovdd 13802-096 figure 96 . power consumption per channel vs. supply voltage , low power mode 25 20 10 15 5 0 power dissipation (mw) C40 120 temperature (c) C20 0 20 40 60 80 100 avdd1x avdd2x avdd4 iovdd 13802-097 figure 97 . power dissipation vs. temperature, low power mode
ad7771 data sheet rev. 0 | page 32 of 98 terminology common - mode rejection ratio (cmrr) cmrr is the ratio of the power in the adc output at full - scale frequency, f, to the power of a 100 mv p - p sine wave applied to the common - mode voltage of ainx+ and ainx? at frequency, f s . cmrr (db) = 10 log( pf / pf s ) where: pf is the power at frequency, f , i n the adc output. pf s is the power at frequency, f s , in the adc output. differential nonlinearity (dnl) error in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. dnl error is often specified in terms of resolution for which no missing codes are guaranteed. integral nonlinearity (inl) error integral non l inearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is a level 1? lsb beyond the last code tr ansition. the deviation is meas ured from the middle of each code to the true straight line. dynami c range dynamic range is the rat io of the rms value of the full - scale input signal to the rms noise measured for an input . the value for dynamic range is expressed in decibels . channel to channel isolation channel to channel isolation is a measure of the level of crosstalk between channels. it is measured by applying a full - scale frequency sweep sine wave signal to all seven un selected input channels and determining how much that signal is attenuated in the se lected ch annel. the value is given for worst case scenarios across all eight channels of the ad7771 . intermodulation distortion with inputs consisting of sine waves at two frequencies, f a and f b , any active device with nonlinearities creates distortion products at the sum and difference frequencies of mf a and nf b , where m, n = 0,1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n are equal to 0. for example, the second - order terms include ( f a + f b ) and ( f a ? f b a nd the third - order terms include (2 f a + f b ), (2 f a ? f b ), ( f a + 2 f b ), and ( f a ? 2 f b ). the ad7771 is tested using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the second - order terms are usually dista nced in frequency from the original sine waves, and the third - order term s are usually at a frequency close to the input frequencies. as a result, the second - order and third - orde r terms are specified separately. the calculation of the intermodulation distor tion is per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals , expressed in decibels. gain error the first transition (from 100 000 to 100 001) occur s at a level ? lsb above nominal negative full scale (? 2.49999 v for the 2.5 v range). the last transition (from 011 110 to 011 111) occur s for an analog voltage 1? lsb below the nominal full scale ( 2.49999 v for the 2.5 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. gain error drift gain error drift is t he ratio of the gain error change due to a tempera ture change of 1c and the full - scale range (2 n ). it is expr essed in ppm/c . least significant bit (lsb) the least significant bit, or lsb, is the smallest increment that ca n be represented by a converter. for a fully differential input adc with n bits of resolution, the lsb expressed in volts is lsb (v) = n ref v 2 2 lsb ( v in ) = n gain ref pga v 2 2 power supply rejection ratio (psrr) variations in power supply affect the full - scale transition but n ot the linearity of the converter. psrr is the maximum change in the full - scale transition point due to a change in the power supply voltage from the nominal value. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist f requency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - (noise + distortion) ratio (sinad) s inad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. spurious - free dynamic range (sfdr ) sfdr is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal including harmonics. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels.
data sheet ad7771 rev. 0 | page 33 of 98 offset error offset error is the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. offset error drift offset error drift is t he ratio of the offset error change due to a tempera ture change of 1c and the full - scale code range (2 n ). it is expressed in v/c .
ad7771 data sheet rev. 0 | page 34 of 98 theory of operation the ad7771 is an 8 - channel , simultaneo usly sampling , low noise , 24- bit - adc with integrated digital filtering per channel and src . the ad7771 offers two operation modes: high resolution mode , which offers up to 128 k sps , and low power mode, which offers up to 32 k sps . the ad7771 employs a - c onversion technique to convert the analog input signal into an equivalent digital word. the overview of the - technique is that the modulator samples the input waveform and outputs an equivalent digital word at the input clock frequency, f clkin . due to the high oversampling rate , this technique spreads the quantization noise from 0 hz to f clkin /2 (in the case of the ad7771 , f clkin relates to the external clock); therefore , the noise energy con tained in the band of interest is reduced (see figure 98 ). to further reduce the quantization noise, a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the band of interest (see figure 99). the digital filter th at follows the modulator removes the large out of band quantization noise (see figure 100) . f or more information on basic and advanced concepts of - adcs , see the mt - 0 22 tutorial and mt - 023 tutorial . digital filtering has certain advantages over analog filtering. because digit al filtering occurs after the analog - to - digital conversion process, it can remove nois e injected during the conversion. analog filtering cannot remove noise injected during conversion. quantization noise f clkin /2 band of interest 13802-098 figure 98 . - adc operation, reduction of noise energy c ontained in the band of interest (linear scale x - axis ) f clkin /2 noise shaping band of interest 13802-099 figure 99 . - adc operation, maority of noise energy shifted out of the band of interest (linear scale x - axis) f clkin /2 band of interest digital filter cutoff frequency 13802-100 figure 100 . - adc operation , removal of noise energy from the band of interest (linear scale x - a xis) the - adc starts the conversions of the input signal after the supplies genera ted by the internal ldo regulator s become stable. an external signal is not required to generate the conversions. a nalog inputs the ad7771 can be operated in bipolar or unipolar modes and accepts true differential, pseudo differential, and single - ended input signals, as shown in figure 101 through figure 104. table 10 summarizes th e maximum differential input signal and dynamic range for the different input modes . table 10 . input signal modes input signal mode pga g ain maximum differential signal maximum p eak - to - peak signal true differential all gains ( v ref /pga gain ) 2 v ref / pga gain pseudo differential all gains ( v ref /pga gain ) 2 v ref / pga gain single - ended all gains v ref /pga gain v ref /pga gain
data sheet ad7771 rev. 0 | page 35 of 98 bipolar or unipolar true differential avdd1x C 0.1v ainx+ ainx+ avssx + 0.1v vcm v ref /pga gain 13802-101 figure 101 . - adc input signal configuration , true differential bipolar or unipolar pseudo differential avdd1x C 0.1v ainx+ ainx+ avssx + 0.1v vcm v ref /pga gain 13802-102 figure 102 . - adc input signal configuration , pseudo differential bipolar single-ended ainx+ ainx+ avssx + 0.1v v ref /pga gain 13802-103 figure 103 . - adc input signal configuration, single - ended bipolar v ref /pga gain unipolar single-ended ainx+ ainx+ + 0.1v 13802-104 figure 104 . - adc input signal configuration, single - ended unipolar the common mode input signal is not limited, but keep the absolute input signal voltage on any ainx pin between avssx + 100 mv and avdd1x ? 100 mv; otherwise , the input signal linearity degrades and , if the signal voltage exceed s the absolute maximum signal rating , damage s the device . figure 105 shows the m ax imum and minimum voltage common - mode range at different pga gains for a maximum differential input voltage . common-mode voltage (v) 1.6500 1.2375 0.8250 0.4125 (avdd1x + avssx)/2 C0.4125 pga gain 2 4 8 1 C0.8250 C1.2375 C1.6500 v ref = 2.5v avdd1x = 1.65v avssx = C1.65v true differential pseudo differential 13802-105 figure 105 . maximum common - mode voltage range for a maximum differential input signal the ad7771 provides a common - mode voltage pin ( avdd1 x + avss x )/2 ) , vcm, for the single - supply, pseudo differentia l, or true differential input configurations. transfer function the ad7771 can operate with up to a 3.6 v reference, typical at 2.5 v, a n d convert s the differential voltage between the analog inputs (ain x + and ain x ?) into a digital output. the adc convert s the voltage difference between the analog input pins (ainx+ ? ainx?) into a digital code on the output. the 24 - bit conversion result is in msb fir st , twos complement format, as shown in table 11 and figure 106 . table 11. output codes and ideal input voltages for pga = 1 condition analog input ( ( ainx+ ) ? ( ainx ?) ) , v ref = 2.5 v digital output code , twos complement (hex adecimal ) fs ? 1 lsb +2.499999702 v 0x7fffff midscale + 1 lsb +298 nv 0x000001 midscale 0 v 0x000000 midscale ? 1 lsb ?298 nv 0xffffff ?fs + 1 lsb ?2.499999702 v 0x800001 ?fs ?2.5 v 0x800000 100 ... 000 100 ... 001 100 ... 010 011 ... 101 011 ... 110 011 ... 111 adc code (twos complement) analog input +fsr C 1.5lsb +fsr C 1lsb Cfsr + 1lsb Cfsr Cfsr + 0.5lsb 13802-106 figure 106 . transfer function
ad7771 data sheet rev. 0 | page 36 of 98 mclk start - modulator signal chain for channel x control block pin control control option pin or spi digital filter sinc3/ sinc5 src gain scaling and offset correction conversion data interface mode0 to mode3 cs sclk sdo sdi sync_out sync_in reset drdy doutx dclk format0 and format1 ainx+ pga gain 1, 2, 4, 8 esd protection ainxC spi control 13802-107 figure 107 . top level core signal chain core signal chain each - adc channel on the ad7771 has an identical signal path from the analog input pins to the digital output pins. figure 107 shows a top l evel implementation of this signal chain . prior to each - adc , a pga map s sensor outputs into the adc inputs, providing low input current in dc ( 8 na , input current , and 2 n a differential input current for high resolution mode ), an 8 pf input capacitance in ac, and configurable gains of 1, 2, 4, and 8 . see the an - 1392 application note for more information. each adc channel has its own - modulator, which oversamples the analog input and passes the digital representation to the digital filter block. the data is filtered, scaled for gain and offset , and is then output on the data interface. to minimize power consumption, the channels can be individually disabled. capacitive pga each - adc has a dedicated pga, offering gain ranges of 1, 2, 4, and 8. this pga reduces the need for an external input buffer and allows the user to amplify small sensor signals to use the full dynamic range of the ad7771 . the pga maximize s the signal chain dyn amic range for small sensor output signals. the ad7771 uses chopping of the pga to minimize offset and offset drift in the input amplifier , reducing the 1/f noise as well . for the ad7771 , the chopping frequency is set to 128 k hz for high resolution mode , a nd 32 khz for low power mode ( see the an - 1392 application note for more informatio n) . the chopping tone is rejected by the sinc3 or sinc5 filter s . to minimize intermodulation effects that may cause an i mage in the band of interest, it is recommended to limit the input signal bandwidth to 2/3 of the chop frequency. the capacitive pga common - mode voltage does not depend on the gain, and can be any value as long as the input signal voltage is within avssx + 100 mv to avdd1x ? 100 mv. see figure 105 for the maximum common - mode voltage at maximum differential input signals. internal reference a nd reference b uffers the ad7771 integrates a 2.5 v, 1 0 ppm /c ( typical ) , voltage reference that is disabled at power - up. t he buffered reference is available at pin 49 and offers up to 10 ma of continuous current. a 10 0 nf capacitor is required if the reference is enabled. in applications where a low noise reference is required, it is recommende d to add a low - pass filter (lpf) with a cutoff frequency (f cutoff ) below 10 hz to the ref_out pin. connect the output of this filter to refx+, and connect avssx to refx?. in this scenario, configure the - reference as external. an example of performance with and without the output filter is shown in figure 108 . 115 105 95 85 75 snr (db) 0.05 0.50 1.00 2.00 2.50 differential input voltage (v) v ref = internal reference f cutoff = 10hz 13802-108 figure 108 . snr adding external lpf with v ref = internal reference and f c utoff = 10 hz the ad7771 can be used with an external reference connected between the refx+ and refx? pins. recommended reference volt age sources for the ad7771 include the adr44 1 and adr45 25 family of low noise, high accuracy voltage references.
data sheet ad7771 rev. 0 | page 37 of 98 adc modulator sinc filter data interface control mclk divider high resolution mode: mclk/4 low power mode: mclk/8 dclk divider 1, 2, 4, 8, 16, 32, 64, 128 dec rates = 16, 32, 64, 128, 256, 512, 1024, 2048, 4095.99 mod_mclk dclkx drdy dout3 to dout0 pga ainx+ mclk ainxC 13802-109 figure 109 . clock generation on the ad7771 the reference buffers can be ope rated in three different modes: buffer enabled mode, buffer bypassed mode, and buffer precharged mode. i n buffer enabled mode , the buffer is fully enable d , minimizing the current requirements fr om the external references. note that the buf fer output voltage headroom is 100 mv from the rails. in buffer bypassed mode, t he external reference is directly connected to the adc reference cap acitor s ; the reference must provide enough current to correctly charge the internal adc reference capacitors . in this mode of operation, a degradation in crosstalk is expected because the adc channels are not isolated from each other . buffer precharged ( pre - q) mode is the default operation mode. it is a hybrid mode where the internal reference buffers are connected during the initial acquisition time to pre charge the internal adc reference capacitors . during the final phase of the acquisition , the reference is connected directly to the adc c apacitors . this mode has some benefits compared to the buffer enabled and buffer bypassed modes. in buffer pre - q mode, the reference current requirements are minimized compared to buffer bypassed mode and the noise contribution from the internal reference buffers is removed ( compared to buffer enabled mode ) . in buffer pre - q mode , the headroom/footroom of the buffer reference is not applicable because the reference sets the final voltage in the adc reference capacitors . integrated ldo s the ad7771 has three internal ldo s to regulate the internal supplies: two ldos for the analog block and one ldo for the digital core. the internal ldos requires an external 1 f decoupling capacitor on the dregcap, areg1cap, and the areg2cap pins. the ldo slew rate may be low because it depends on the main supply slew rate; therefore, a hardware reset generated by pulsi ng the reset pin at power - up is required to guarantee that the digital block initializes correctly . clocking and samplin g the ad7771 includes eight - adc cores. each adc receive s the same master clock signal. the ad7771 requires a maximum external mclk frequency of 8192 khz for high resolution mode and 4096 khz for low power mode . the mclk is internally divided by 4 in high per formance mode and by 8 in low power mode to produce the modulator mclk ( mod_mclk ) signal used as the modulator sampling clock for the adcs. the mclk can be decreased to accommodate lower odrs if the minimum odr selected by the sinc3 filter is not low enoug h. if the external clock is lower than 250 khz, set the clk_qual_dis bit (in spi control mode only ) . the ad7771 integrates an internal oscillator clock that initialize s the internal register s at power - up. the clk_ sel pin defines the external c lock used after initialization ( see table 12) . table 12 . clock sources clk_ sel state clock source connection 0 cmos input to xtal2/mclk, iovdd logic level. xtal1 must be tie d to dgnd . 1 crystal connected between xtal1 and xtal2 /mclk . the mclk signal generate s the dclk output signal , which in turn clock s the - conversion data from the ad7771 , as shown in figure 109. digital reset and sy nchronization p ins an external pulse in the sync_in pin generates the inte rnal reset of the digital block; this pulse does not affect the data programmed in the internal registers. a pulse in this pin is required in two cases as follows : x after updating one or more register s directly related to the sinc filter ( power mode, offset, gain, phase compensation , and sinc filter ). x to s ynchronize multiple devices . the pulse in the sync_in pin must be synchronous with mclk.
ad7771 data sheet rev. 0 | page 38 of 98 t here are two different ways to achieve a synchronous pulse i f the controller/processor cannot generate it as follows : ? a pplying an asynchronous pulse on the start pin, which is then internally synchronized with the extern al mclk clock, and the resulting synchronous signal is output on the sync_out pin. ? trigge r ing the sync_out internally. when the ad7771 is configured in spi control mode, toggling bit 0 in the gen eral _user_ config_2 register generate s a synchronous pulse that is output on the sync_out pin. the sync_in and sync_out pins must be externally connected if internal synchronization is used. if multiple ad7771 devices must be synchronized, the sync_out pin of one device can be connected to multiple devices . this synchronization m ethod requires the use of a common mclk signal for all the ad7771 devices connected, as shown in figure 110. if the start pin is no t used, tie it to dgnd. start sync_in iovdd mclk sync_out start sync_in mclk sync_out nc start sync_in mclk sync_out nc ad7771 ad7771 ad7771 61+521721 logic asynchronous pulse 7//75 61+521721 logic 7//75 61+521721 logic 7//75 mclk iovdd 13802- 1 10 figure 110 . multiple ad7771 devices synchronization digital filtering the ad7771 offers low latency sinc3 and sinc5 filter s . most precision - adcs use sinc filters because the sinc filter s offer a low latency path for applications requiring low bandwidth signals, for example , in control loops or where application specific post processing is required. the di gital filter adds notches at multiple s of the sampling frequency. the digital sinc3 filter i mplements three main n otches, one at the maximum odr ( 128 khz or 32 khz, depending on the power mode ) and another two at the odr frequency selected to stop noise aliasing into the pass band. the sinc5 filter implements five notches, one at the maximum odr (128 khz or 32 khz, depending on the power mode) and another four at the odr frequency selected to stop noise aliasing into the pass band. it is recommended to select the sinc5 digital filter for output data rates higher t han 24 ksps. figure 111 and figure 112 show the typical filter transfer function for the high resolution and low power mode s using a decima tion rate of 32 samples for the sinc3 and sinc5 filters . 0 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 64 32 96 128 160 192 224 256 1g 54810+ 13802- 11 1 sinc3 sinc5 figure 111 . sinc 3/ sinc5 frequency response in h igh r esoltuion m ode 0 C100 C90 C80 C70 C60 C50 C40 C30 C20 C10 0 16 8 24 32 40 48 56 64 1g 54810+ 13802- 1 12 sinc3 sinc5 f 112 . s3/ s5 f r l p m th e sample rate converter feature allows fine tuning of the decimation rate , even for non integer multiples of the decimation ra te . see the sample rate converter (src) section for more information on filter profiles for non integer decimation rates. shutdown mode the ad7771 can be placed in shutdown mode by pulling av dd2 x to ground and connecting 1 m resistance , pulled low, to xtal2/mclk . in this mode, the average current consumption is reduced to 1 m a , as shown in figure 113.
data sheet ad7771 rev. 0 | page 39 of 98 C40 C0.5 0 0.5 1.0 10 temperature (c) 60 125 i avdd1x i avdd2x i avdd4 i iovdd avddx = 3.3v iovdd = 3.3v supply current (ma) 13802- 1 13 figure 113 . shutdown current controlling the ad 7771 the ad7771 can be controlled using either pin control mode or spi control mode . pin control mode allows the ad7771 to be hardwired to predefined settings that offer a subset of the over all functionality of the ad7771 . in this mode, the src and diagnostic features or extended errors source are not available. controlling the ad7771 over the spi allows the user access to the full monitoring, diagnostic , and - control functionality. spi control offers additional functionality such as offset, gain , and phase corre ction per channel , in addition to access to the flexible s rc to achieve a coherent sampling. see table 13 for more details about these different configurations. p in control mode in pin control mode, the ad7771 is configured at power - up based on the level of the mode pins, mode0, mode1, mode2 , and mode3. these four pins set the following functions on the ad7771 : the mode of operation, the decimation rate/odr, the pga gain, and the reference source, as shown in table 14. due to the limited number of mode pins and the number of options available, the pga gain control is grouped into blocks of 4, and the odr is selected for the maximum value defined by the decimation rate; odr (khz) = 2048/decimation for high resolution mode, and odr (khz) = 512/decimation for l ow power mode. depending on the mode selected, the device is configured to use an external or an internal reference. the conversion data can be read back using the spi or the data output interface , as shown in table 13 . if the data output interfac e is used to read back the data f r o m the conversions, t he number of dout x lines enabled and the number of clocks required for the - data transfer are deter mined by the logic level of the conv st _sar , format 0 , and format 1 pins . in this case, the dclk2, dclk1 , and dclk0 pins select the - output interface and control the dclk x divide function, which is a submultiple of mclk, as shown in table 15 . the dclk x div ide function sets the frequency of the data output interface dclk x signal. the dclk minimum frequency depends on the decimation rate and operation mode. see the data output interface section for more details about the minimum dclk x frequency. all the pins that define the ad7771 configuration mode are re evaluated each time the sync_in pin is pulsed. t he t ypical connection diagram for pin control mode is shown in figure 114 . table 13. format of the data interface conv st _sar state format 1 format 0 control mode data output mode 1 0 0 pin spi output 0 1 pin spi output 1 1 pin spi output 1 1 spi defined in register 0x014 0 0 0 pin dout0, channel 0 and channel 1 dout1, channel 2 and channel 3 dout2, channel 4 and channel 5 dout3, channel 6 and channel 7 0 1 pin dout0, channel 0 to channel 3 dout1, channel 4 to channel 7 1 0 pin dout0, channel 0 to channel 7 1 1 spi defined in register 0x014
ad7771 data sheet rev. 0 | page 40 of 98 table 14 . pin control mode options pin state decimation rate power mode pga gain channel reference source filter mode3 mode2 mode1 mode0 channel 0 to channel 3 channel 4 to channel 7 0 0 0 0 16 high r esolution 1 1 external s inc5 0 0 0 1 16 high resolution 1 4 external sinc5 0 0 1 0 32 high resolution 1 1 external sinc5 0 0 1 1 32 high resolution 1 4 external sinc5 0 1 0 0 64 high resolution 1 1 external sinc5 0 1 0 1 64 high resolution 1 4 external sinc5 0 1 1 0 128 high resolution 1 1 external sinc5 0 1 1 1 128 high resolution 1 4 external sinc5 1 0 0 0 256 high resolution 1 1 external sinc5 1 0 0 1 16 high resolution 1 1 internal sinc5 1 0 1 0 32 high resolution 1 1 internal sinc5 1 0 1 1 64 high resolution 1 1 internal sinc5 1 1 0 0 16 low power 1 1 external sinc5 1 1 0 1 32 low power 1 1 external sinc5 1 1 1 0 64 low power 1 1 external sinc3 1 1 1 1 32 low power 1 1 external sinc3 table 15 . dclk x select ion for pin control mode state dclk2/sclk dclk1/sdi dclk0/sdo mclk divider 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128
data sheet ad7771 rev. 0 | page 41 of 98 adc data serial interface spi control interface fpga or dsp avdd 3.3v external reference avssx avssx ain7+ ain7C ain0+ ain0C pga vcm avdd1x buffer buffer ad7771 dregcap convst_sar mode3 to mode0 refx+ refxC ref_out avdd4 avssx avssx avdd2x avdd3.3v avdd3.3v iovdd 2v to 3.6v avssx aregxcap avssx avssx iovdd 24-bit - adc sinc3/sinc5 src sync_in drdy sync_out start reset dclk cs sclk sdo clk_sel xtal2 dclk2 to dclk0 xtal1 dout0 dout1 spi/sport slave interface dout2 dout3 spi master interface pga vcm sdi format1 and format0 clock source 13802- 1 14 figure 114 . pin control mode connec tion diagram with external reference adc data serial interface spi control interface fpga or dsp avdd 3.3v avssx avssx ain7+ ain7C ain0+ ain0C pga vcm avdd1x buffer full buffer buffer ad7771 dregcap convst_sar gpio2 to gpio0 refx+ refxC ref_out avdd4 avssx avdd2x avdd3.3v iovdd 2v to 3.6v avssx aregxcap avssx avssx iovdd auxain+ auxainC 24-bit - adc 12-bit sar adc mux diagnostic inputs sinc3/sinc5 src sync_in drdy sync_out start reset dclk cs sclk sdo sdi clk_sel format0 xtal2 format1 iovdd iovdd xtal1 dout0 dout1 spi/sport slave interface dout2 dout3 spi master interface pga vcm clock source 13802- 1 15 figure 115 . spi control mode connection diagram with internal reference
ad7771 data sheet rev. 0 | page 42 of 98 spi c ontrol the second option for control and monitoring the ad7771 is via the spi . this option allows access to the full functionality on the ad7771 , including access to the sar converter, phase synchronization, offset and gain a djustment, diagnostics , and the src . to use the spi control , set the format0 and format 1 pins to logic high. in this mode, the spi can also read the - conversati on data by setting the spi_slave _ mode_en bit. t he t ypical connection diagram for spi control mode is shown in figure 115. functionality available i n spi control mo de spi control of the ad7771 offers the super set of the functions and diagnostics. the spi control functionality section describes the functionality and diagnostics offered when in spi control mode. offset and gain correction offset and gain registers are available for system calibration. the gain regis ter is preprogrammed during final production for a pga gain of 1, but can be overwritten with a new value if required. the gain register is 24 bits long and is split across three registers , chx_gain_upper_byte, chx_gain_mid_byte, and chx_gain_lower_byte, w hich set the gain on a per channel basis. the gain value is relative to 0x555555, which represents a gain of 1. the offset register is 24 bits long and is spread across three byte registers, chx_offset_upper_byte, chx_offset_mid_ byte, and chx_offset_lowe r_byte. the default value is 0x000000 at power - up. program the offset as a twos complement , signed 24 - bit number. if the channel gain is set to its nominal value of 0x555555, an lsb of offset register adjustment changes the digital output by ? 4/3 lsbs . as an example of calibration, the offset measured is ?200 lsb (with both ainx pins connected to the same potential). an offset adjustment of ? 150 lsb change s the digital output by ?150 (? 4/3) = 200 lsbs (gain value = 0x555555), representing this number as two complement, 0xffffff ? 0x96 + 1 = 0xffff70. program the offset register as follows: ? chx_offset_upper_byte = 0xff ? chx_offset_mid_byte = 0xff ? chx_offset_lower_byte = 0x70 note that the offset compensation is performed before the gain compensation. the gain is programmed during final test ing for pga gain = 1. the gain register value s can be overwritten; however , after a reset or power cycle, the gain register values revert to the hard coded progr ammed factory setting. if the gain required is 0.75 of the nominal value (0x555555), the value that must be programmed is 0x555555 0.75 = 0x400000 then, a n lsb of the offset register adjustment changes the digital output by ? 4/3 0.75 = 1 lsb. program the gain register as follows: ? chx_gain_upper_byte = 0x40 ? chx_gain_mid_byte = 0x00 ? chx_gain_lower_byte = 0x00 spi control functionality global control functions the following list details the global control functions of the ad7771 : ? high resolution a nd low power modes of operation ? o dr : src ? sinc 3 and sinc5 filter s ? vcm buffer power - down ? internal/ external reference selection ? enable, pre - q , or bypassed reference buffer modes ? internal r eference power - down ? sar diagnostic mux ? sar power - down ? gpio write/read ? spi sar conversion readback ? spi slave mode read - results ? sdo and dout x drive strength ? dout x mode ? dclk division ? internal ldo bypassed ? cyclic redundancy check ( crc ) protection : enable d or disable d per channel functions the following list details the per channel f unctions of the ad7771 : ? pga gain . ? - channel power - down. ? phase delay: synchronization phase offset per channel . ? calibration of offset . ? calibration of gain . ? - input signal mux. ? channel error register . ? pga gain . phase adjustment the ad7771 phase delay can be adjusted to compensate for phase mismatches between chan nels due to sensors or signal channel phase errors connected to the ad7771 . achieve phase adjustment by programming the chx_sync_offset register. this programming de lays the synchr onization signa l by a certain number of modulator clocks ( mod_ m clk ) to i ndividually initiate the digital filter for each - adc. the phase adjustment register is read during the pulse; conse - quently, any further changes on the register have no effect unle s s a pulse is generated (see the digital reset and synchronization
data sheet ad7771 rev. 0 | page 43 of 98 pins section for more information on how to generate a pulse in the pin). the phase offset register is multiplied internally by a factor that depends on the decimation rate, as shown in table 16. table 16 . phase adjustment vs. decimation rate phase adjustment compensation decimation rate 1 255 2 511 4 1023 8 2047 16 4095 the maximum phase delay cannot be equal to or greater than the decimation rate. if this is the case, the value changes internally to the decimation rate value minus 1. as an example, the phase mismatch between channel 0 and channel 1 is 5, and the odr is 5 ksps in high resolution mode. in this case, the decimation rat e is 2048 khz/5 khz = 409.6, which means that the offset register value is multiplied internally by 2. assuming an input signal of 50 hz, the number of mod_ mclk pulses required to sample a full period is 2048 khz/ 50 hz = 40960 > 360/40960 = 0.00878 . if a 5 delay is required, the number of mod_mclk delays must be 569 (5/0.00878) because the offset register is multiplied by 2; the final offset register value is 409.6/2 ? 569/2, which gives a negative value. in this case, if the offset value programmed t o the register is higher than 204 (for example, 210 2 = 420), the value is internally changed to 408, resulting in a phase compensation of 408 0.00878 = 3.58. pga gain the pga gain can be selected individually by appropriately select - ing bits[7:6] in the chx_config register, as shown in table 17 . table 17 . pga gain settings via chx_config chx_config , bits [7:6] setting pga gain setting 00 1 01 2 10 4 11 8 if the - reference is updated, it is recommended to apply a pulse on the sync_in pin to remove invalid samples during the transition of the reference . decimation the decimation defines the sam pling frequency as follows: ? in high resolution mode, the sampling frequency = mclk/ (4 decimation) ? in low power mode, the sampling frequency = mclk/ (8 decimation) refer to the sample rate converter (src) section for more information . gpio x pins if the ad7771 operates in spi control mode, the mode pins operate as gpio x pins, as shown in figure 116 . the gpio x pins can be configured as inputs or outputs in any order. register map gpio0 gpio1 gpio2 13802- 1 16 figure 116 . gpio x pin f unctionality configuration control and read back of the gpio x pins are set via bits [2:0] in the gpio_config register (0 = input, 1 = output) and the gpio_data register. among other uses, the gpio s can control an external mux connected to the auxiliary inputs of the sar adc. use this mux to verify the results on the - adc s. in add ition, the gpio x pins can be used to externally trigger a new decimation rate. refer to the sample rate converter (src) section for more information ab out this functionality. - reference configuration the ad7771 can operate with in ternal or external references. i n addition , for dia gnostic purposes, the analog supply can be used as a reference, as shown in table 18. refx?/refx+ allow the selection of a voltage reference where t he refx+ voltage is lower than the voltage on the refx? pin . table 18. - references setting for adc_ mux_config , bits [7:6] channel 0 to channel 3 channel 4 to channel 7 00 ref1+/ ref1? ref2+/ ref2? 01 internal reference internal reference 10 avdd1a/avss1a avdd1b/avss1b 11 ref1?/ ref1+ ref2?/ ref2+ reference buffer operation is described in table 19 . the selected reference and buffer operation mode affect all channels. if the - reference is updated, it is recommended to apply a pulse on the sync_in pin to remove invalid samples during the transition of the reference .
ad7771 data sheet rev. 0 | page 44 of 98 table 19 . reference buffer operation modes reference buffer operation mode refx+ refx? enable d buff er_config_1, bit 4 = 1; buff er_config_2 , bit 7 = 0 buffer_config_1, bi t 3 = 1; buffer_config_2, bit 6 = 0 prec harge d buffer_config_1 , bit 4 = 1; buf fer_config_2, bit 7 = 1 buffer_config_1 , bit 3 = 1; b uffer_config_2, bit 6 = 1 disable d buffer_config_1 , bit 4 = 0 buffer_config_1 , bit 3 = 0 table 20 . additional disable power- down blocks block register notes vcm general_user_config _ 1, bit 5 enable d by default reference buffer buffer_config_1 , bits [4:3] prec harge mode by de f ault internal reference buffer general _user_config _ 1, bit 4 disable d by default - channel ch_disable , bits [7:0] all channels enable d sar general_user_config _ 1, bit 3 disable d by default internal oscillator general_user_config _ 1, bit 2 enable d by default power modes the ad7771 offers different power modes to improve the power efficiency , high resolution and low power mode , which can be controlled via general_user_config _ 1, bit 6 . to further reduce the power , additional blocks can be disabled independently, as described in table 20. if the power mode changes, a pulse on the sync_in pin is required. sinc 3 and sinc5 filters the ad7771 implements sinc 3 and sinc 5 digital filters. by default, the device power s up with the sinc 3 f ilter, but it can be change d by setting general_user_config_2 , bit 6. if the sinc filter is change d , a pulse in the sync_in pin is required. ldo bypassing the internal ldos can be individually bypassed and an externa l supply can be applied directly to the areg1cap, areg2cap, or dregcap pin. table 21 shows the absolute minimum and maximum supplies for these pins, as well as the associated register used to bypass the regulator. table 21 . ldo bypassing ldo buffer_config_2, bits[ 2:0] 1 supply max (v) min (v) areg1cap 1xx 1.9 1.85 areg2cap x1x 1.9 1.85 dregcap xx1 1.9 1.65 1 x means dont care. digital spi the spi serial interface on the ad7771 consists of four signals: cs , sdi, sclk , and sdo . a typical connection diagram of the spi is shown in figure 117. dsp/fpga ad7771 cs sclk sdi sdo 13802- 1 17 figure 117 . spi control interface ad7771 is the spi slave, digital signal processor (dsp)/ f ield programmable gate array (f pga ) is the master the spi s operates in m ode 0 and mode 3, cpol = 0, cpha = 0 (mode 0) or cpol = 1, cpha = 1 (mode 3). in pin control mode , the sdi can read back the - results, depending on the level of the conv st _s ar pin , as described in table 13. in spi control mode , the spi transfer s data into the on - chip registers while the sdo pin read s back data from the o n - chip registers or read s the sar or the - conversions results, depending on the selected operation mode. the sdo data source in spi control mode is defined by the general_user_config _ 2 and general_user_ config _ 3 registers, as described in table 22. table 22 . spi operation mode in spi control mode general_user_ config _ 2, bit 5 setting general_user_ config _ 3, bit 4 setting 1 mode 0 0 internal register 0 1 - data conversion 1 x sar conversion 1 x means dont care.
data sheet ad7771 rev. 0 | page 45 of 98 in spi control mode, there are four different levels of input/ output ( i/o ) strength on the sdo pin that can be selected in general_user_config _ 2 , bits [4:3], as described in table 23 . table 23 . sdo strength general_user_config _ 2 , bits [4:3] setting mode 00 nominal 01 strong 10 weak 11 extra strong sclk is the serial clock input for the device. a ll data transfers (on either sdo or sdi) occur with respect to this sclk signal. the spi can operate in multiple s of eight bits. for example, i n spi control mode, if the sdo pin is used to read back the data from the internal register or the sar adc, the data frame is 16 bits wide (crc disable d ), as shown in figure 118 , or 24 bits wide (crc e nable d ), as shown in figure 119 . in this case, the controll er can generate one frame of 16 bits or 24 bits (w ith and without the crc enabled ) , or two o r three frames of 8 bits ( with and without the crc enabled ) . when the sdo pin read s back the data from the - channels, 64 bits must be read back from the controller (i n this case , the contro ller can generate a frame of 64 bits either 2 32 bits, 4 16 bits, or 8 8 bits ) . spi crc checksum protection (spi control mode) the ad7771 has a checksum mode that improve s spi robustness in spi control mode . using the checksum ensures that only valid data is written to a register and allows data read from the dev ice to be validated . the spi crc can be enable d by setting the spi_crc_test_en bit . if an error occurs during a register write, the spi_crc_err is set in the error register. e nabling the spi_crc_test_en bit results in a crc checksum being performed on all the r/ w operations. when spi_crc_ test_en is enabled, an 8 - bit crc word is appended to every spi transaction for sar and register map operations. for more information on - readback operations, see the crc header section. to e nsur e that the register write is successful, it is recommended to read back the register and verify the checksum. for crc checksum calculations, the following polynomial is always used: x 8 + x 2 + x + 1. see the spi control mode checksum s ection for more information . spi read/write register mode (spi control mode ) the ad7771 has on - board registers to configure and control the device. the registers have 7 - bit address es the 7 - bit register address on the sdi line select s the register for the read/write funct ion. the 7 - bit register address follows the r/ w bit in the sdi data. the 8 bits on the sdi line following the 7 - bit register address are the data to be written to the selected register if the spi is a write transfer. data on the sdi line is clocked into the ad7771 on the rising edge of sclk, as shown in figure 3 . the data on the sdo line during the spi transfer contain s the 8 - bit 00 10 0000 header: 8 bits of register data in the case of a read (r) operation , or 8 zero s in the case of a write ( w ) operation . with the crc disabled, the basic data frame on the sdi line during the transfer is 16 bits long, as shown in figure 118. when the crc is enabled , a minimum frame length of 24 sclk periods are required on spi transfers. the 24 bits of data on the sdo line c ons ist of an 8 - bit header ( 00 10 0000), 8 bits of data , and an 8 - bi t crc ( see figure 119) . r/w a6 a5 a4 a3 a2 a1 a0 d6 d7 d5 d4 d3 d2 d1 d0 0 sdo cs sclk sdi 0 1 0 0 0 0 0 r7 r6 r5 r4 r3 r2 r1 r0 13802- 1 18 figure 118 . 16 - bit spi transfer crc disabled r/w a6 a5 a4 a3 a2 a1 a0 d6 d7 d5 d4 d3 d2 d1 d0 i crc7 i crc6 i crc5 i crc4 i crc3 i crc2 i crc1 i crc0 0 sdo cs sclk sdi 0 1 0 0 0 0 0 r7 r6 r5 r4 r3 r2 r1 r0 i crc7 i crc6 i crc5 i crc4 i crc3 i crc2 i crc1 i crc0 13802-119 figure 119 . 24 - bit spi transfer crc enabled
ad7771 data sheet rev. 0 | page 46 of 98 spi sar diagnostic mode (spi control mode) setting bit 5 in the general_user_config _ 2 register configures the sdo line to shift out data from the sar adc conversions, as described in table 22. in sar mode, the ad7771 internal registers can be written to , but any readback command is ignored because the sdo data frame is dedicated to shift out the conversion results from the sar adc. to exit this mode of operation , reset bit 5 in the general_ user_config _ 2 register. the data on the sdo line during the spi t ransfer contains a 4 - bit 0010 header and the 12- bit sar conversion result if the crc is disabled . when the crc is enabled, a minimum frame length of 24 sclk periods is required on spi transfers. the 24 bits of data on the sdo line consist of a 4 - bit heade r (0010), the 12- bit data, and an 8 - bit crc, as shown in figure 120. p er the spi read/write register mode (see the spi read/write register mode section), the sdi line contains the r/ w bit, a 7 - bit register address, the 8 - bit data , and an 8 - bit crc (if enable d ). to avoid unwanted w rites to the internal register while the sar conversions are read back through the sdo line, it is recom - mended to send a readback command, for example, 0x8000, to the device , which is ignored bec a u s e the sdo pin shift s out the content of the sar adc. if consecutive conversion s are performed in the sar adc , read back the result from the previous conversion before a new conversion is generated. o therwise , the results are corrupted. - d ata, adc mode in pin control mode, the spi can be used to read back the - conversions as described in table 13. in spi control m ode, the spi read s back the - con versions by setting general _ user_ config _ 3, bit 4, as described in table 22 ; in this mode, the ad7771 inter nal register can be written to , but any readback command is ignore d because the sdo data frame is dedicated to shifting out the conversion results from the - adcs. to avoid unwanted writes to the internal r egister, it is recommended to send a readback command, for example, 0x8000 , to the device , which is ignored because the sdo pin shift s out the content of the - adc. the sdo pin data can be read back in any multiple of 8 bits, for example, as 64 bits, 2 32 bits, 4 16 bits, or 8 8 bits. spi software reset keeping the sdi pin high during 64 consecutives clocks generate s a software reset. r/w a6 a5 a4 a3 a2 a1 a0 d6 d7 d5 d4 d3 d2 d1 d0 i crc7 i crc6 i crc5 i crc4 i crc3 i crc2 i crc1 i crc0 0 sdo cs sclk sdi 0 1 0 sar 11 sar 10 sar 9 sar 8 sar 6 sar 7 sar 5 sar 4 sar 3 sar 2 sar 1 sar 0 i crc7 i crc6 i crc5 i crc4 i crc3 i crc2 i crc1 i crc0 13802-120 figure 120 . sar adc/diagnostic mode crc enabled
data sheet ad7771 rev. 0 | page 47 of 98 rms noise and resolu tion table 24 through table 27 show the dynamic range (dr), rms noise (rti), effective number of bits (enob), and effective resolution (er) of the ad7771 for various output data rates and gain setting s. the numbers given are for the bipolar input range with an external 2.5 v reference. these numbers are typical and are generated with a differential input voltage of 0 v when the adc is continuously converting on a single channel. it is important to not e that the effective resolution is calculated using the rms noise; 16,384 consecutives samples were used to calculate the rms noise. effective resolution = log2( input range / rms noise ) enob = ( dr ? 1.78)/6 high resolution mode table 24 . dr and rti for high resolution mode sinc filter decimation rate output data rate (sps) f ?3 db (hz) gain = 1 gain = 2 gain = 4 gain = 8 dr (db) rti (v rms) dr (db) rti (v rms) dr (db) rti (v rms) dr (db) rti (v rms) sinc5 16 128,000 26542.34 95.1 31.32 91. 7 22.68 87.1 19.39 82. 0 17.11 32 64,000 13403.14 101.8 14.31 98.5 10.30 94.4 8.41 89.7 7.37 64 32,000 6833.54 107.1 7.90 105.3 4.85 101.5 3.65 96.9 3.14 256 8,000 1906.34 114. 4 3.34 113.8 1.84 111.6 1.16 107.9 0.91 sinc3 128 16,000 4878.83 105. 7 9.01 105. 2 4.88 103. 2 2.99 99. 6 2.26 256 8,000 2756.43 112. 1 4.32 111.5 2.31 109.3 1.52 105.5 1.19 512 4,000 1695.23 115. 8 2.86 115.6 1.51 113.5 0.96 109.5 0.75 1024 1,000 899.33 122. 0 1.39 121.6 0.73 119.6 0.47 115.7 0.36 table 25 . enob and er for high resolution mode sinc filter decimation rate output data rate (sps) f ?3 db (hz) gain = 1 gain = 2 gain = 4 gain = 8 enob (bits) er (bits) enob (bits) er (bits) enob (bits) er (bits) enob (bits) er (bits) sinc 5 16 128,000 26542.34 15.5 17.3 14.9 17.8 14.2 18.0 13.3 18.2 32 64,000 13403.14 16.6 18.4 16.1 18.9 15.4 19.2 14.6 19.4 64 32,000 6833.54 17.5 19.3 17.2 20.0 16.6 20.4 15.8 20.6 256 8,000 1906.34 18.7 20.5 18.6 21.4 18.2 22.0 17.6 22.4 sinc 3 128 16,000 4878.83 17.3 19.1 17.2 20.0 16.9 20.7 16.3 21.1 256 8,000 2756.43 18.3 20.1 18.2 21.0 17.9 21.6 17.2 22.0 512 4,000 1695.23 18.9 20.7 18.9 21.7 18.6 22.3 17.9 22.7 1024 1,000 899.33 20.0 21.8 19.9 22.7 19.6 23.3 18.9 23.7
ad7771 data sheet rev. 0 | page 48 of 98 lo w power mode table 26 . dr and rti for low power mode sinc filter decimation rate output data rate (sps) f ?3 db (hz) gain = 1 gain = 2 gain = 4 gain = 8 dr (db) rti (v rms) dr (db) rti (v rms) dr (db) rti (v rms) dr (db) rti (v rms) sinc5 16 32,000 6833.54 94.3 34.2 90. 9 25.04 86. 5 20.5 81. 3 19.43 32 16,000 3548.74 100. 9 15.7 97.8 11.22 93.6 9.0 87.9 8.39 64 8,000 1906.34 106. 7 83.3 104.6 5.18 100.6 4.03 96.1 3.46 512 1,000 469.24 117. 1 25.2 116.8 1.29 114.4 8.41 110.7 0.67 sinc3 64 8,000 2756.43 95. 5 29.86 9 5.0 15.26 93. 7 8.9 90. 8 6.11 128 4,000 1695.23 105. 4 9.47 105.1 4.95 102.7 3.21 98.7 2.51 256 2,000 1164.63 111. 7 4.62 111.2 2.41 108.9 1.57 104.8 1.27 1024 500 766.68 118. 6 2.1 118.2 1.07 116.2 0.7 112.5 0.54 table 27. enob and er for low power mode sinc filter decimation rate output data rate (sps) f ?3 db (hz) gain = 1 gain = 2 gain = 4 gain = 8 enob (bits) er (bits) enob (bits) er (bits) enob (bits) er (bits) enob (bits) er (bits sinc5 16 32,000 6833.54 15.4 17.2 14.8 17.6 14.1 17.9 13.2 18.0 32 16,000 3548.74 16.5 18.3 16.0 18.8 15.3 19.1 14.3 19.2 64 8000 1906.34 17.4 15.9 17.1 19.9 16.4 20.2 15.7 20.5 512 1000 469.24 19.2 17.6 19.1 21.9 18.7 19.2 18.1 22.8 sinc3 64 8,000 2756.43 15.6 17.4 15.5 18.3 15.3 19.1 14.8 19.6 128 4,000 1695.23 17.2 19.0 17.2 19.9 16.8 20.6 16.1 20.9 256 2,000 1164.63 18.3 20.0 18.2 21.0 17.8 21.6 17.1 21.9 1024 500 766.68 19.4 21.2 19.3 22.2 19.0 22.8 18.4 23.1
data sheet ad7771 rev. 0 | page 49 of 98 diagnostics and monitoring self diagnostics err or the ad7771 includes self diagnostic features to guarantee the correct operation. if an error is detected, the alert pin (pin 18 when using pin control mode or pin 16 when using spi control mode ) is pulled high to generate an external interruption to the controller. in addition, the header of the - output data contain s a n alert bit that inform s the controller of a chip error (s ee the a dc conversion output header and data section). b oth the alert pin and bit ( status header ) are automatically cleared if the error is no longer present. the errors related to the spi do not recover automatically; read back the appropriate register to clear the error . the alert pin and bit reset in the next spi access after the bit is read back . if an error detector is manually disable d , it does not generate an internal error and , cons equently , the register map or the alert pin and bit are not triggered. there are different sources of errors, as described in table 28. in pi n control code, it is not possible to check the error source, and some source s of error are not enable d . in spi control mode, check the source of an error by reading the appropriate register bit. the status_reg _ x register bits identify the register that gene rates an error, as summarized in table 28. table 28 . register error source bit name register source err_loc_gen2 gen_err_reg_2 err_loc_gen1 gen_err_reg_1 err_loc_ch7 ch7_err_reg err_loc_ch6 ch6_err_reg err_loc_ch5 ch5_err_reg err_loc_ch4 ch4_err_reg err_loc_ch3 ch3_err_reg err_loc_ch2 ch2_err_reg err_loc_ch1 ch1_err_reg err_loc_ch0 ch0_err_reg err_loc_sat_ch6_7 ch6_7_sat_err err_loc_sat_ch4_5 ch4_5_sat_err err_loc_sat_ch2_3 ch2_3_sat_err err_loc_sat_ch0_1 ch0_1_sat_err in addition, the status_reg_x registers ha ve a bit that indicates if any internal error bit is set , chip_error . t his bit clears if the error is no longer present and the register is read back. the init_complete bit in the status_reg_3 indicates that the dev ice is initialized correctly. this bit is not an error bit but an indicator. general errors mclk switch error (spi control mode) after power - up , the ad7771 initiates a clocking handover sequence to pass clocking control to the external oscillator, or the cmos clock. in spi control mode, if an error occurs in the handove r , the ext_mclk_switch_err bit is set in the general error register, gen_e rr _reg _ 2. if ext_mclk_switch_err is set , this means that the device is opera ting using t he i nternal oscillator. to use a slow external clock (<265 khz), set the clk_qual_ dis bit. setting this bit also clears the error bit. if the exter nal clock is betwee n 132 khz and 265 khz, depending on the internal synchronization between the internal oscillator and the external clock, the error may not trigger. however, it is still recommended to set the clk_qual_dis bit. if a slow clock is not in use and the error tr iggers, a reset is required. reset detection the ad7771 general error register contains a reset_detected bit. this bit is asserted if a reset pulse is applied to the ad7771 and is cleared by reading the general error register. this bit indicates that the p ower - on reset ( por ) initialized correctly on the device . in addition, this bit can be used to detect an unexpected device reset or glitch on the reset pin. to reset this error signal in spi control mode, toggle the sync_in pin or read from the g eneral error register, gen_err _reg _ 2. to reset this error signal in pin control mode, toggle the sync_in pin. internal ldo status the ad7771 has three internal ldo s to regulate the internal analog an d digital supp ly rails. the ldo s have internal power supply monitors. internal comparators monitor and flag errors with these supplies after they pass a predetermined limit. the aldo1_psm_err, aldo2_psm_err, and dldo_psm_ err bits indicate either a n ldo malfunction , or, if the ldos are bypassed, an incorrect external supply. the internal analog and digital voltage monitors can be disable d by appropriately selecting the ldo_psm_test_en bits . use t he sar adc t o verify the error. additionally, the levels of the inter nal monitors can be manually trigger ed to check i f the detector works correctly by appropriately sett ing the ldo_psm_trip_test_en bits . these bit s increase the comparator window threshold above the ldo outputs , forcing the comparator to trigger. rom and me mory map crc if an error is found at power - up during the rom verification, or if the internal memory map is corrupted, the ad7771 generates a n error and sets memmap_crc_err or rom_ crc_ err, depending on the source of the error. the checker can be disable d by clearing the memmap_ crc_test_en and rom_crc_test_en bits . the device must be reset if any of th ese error s trigger .
ad7771 data sheet rev. 0 | page 50 of 98 - adc errors reference detect ( spi control mode) in spi control mode, the ad7771 includes on - chip circuitry to detect if there is a va lid reference for conversions or calibration s. if the voltage between the selected refx+ and refx ? pins goes below 0.7 v, the ad7771 detects that it no longer has a valid reference . chx_err_ref_det ca n be interrogated to identify the affected channel, which clear s the bit s if the error is no longer present. the voltage detector can be disable d by clearing the ref_det_test_en bit. use t he - adc diagnostic or the sar adc to verify the error. overvoltage and undervoltage events the ad7771 inclu des on - ch ip over voltage/under voltage circuitry on each analog input pin. when the voltage on an analog input pin goes above av dd1x + 0.04 mv , the chx_ err_ainx_ov bit is set. the error disappears if the input voltage falls below avdd1x ? 40 mv . if an under voltage event occurs (avssx ? 4 0 m v ) , the chx_ err_ainx_uv bit is set. the error disappears if the input vo l tage increase s to avssx + 0.04 v . the chx_err_ainm_uv, chx_err_ainm_ov, chx_err_ ainp_uv, and chx_err_ainp_ov bits can be read back to verify the affected channel input, which clear s the bit s if the error is no longer present . the overvoltage and under voltage detection can be disable d independently by clearing the ainm_ uv_test_en, ainm_ov_test_en, ainp_uv_test_en , or ainp_ov_test_en bit . the input voltage can be checked independently with the sar adc. modulator saturation the ad7771 includes modulator satur ation detection on each of the - adc s. if 20 consecutive codes for the modulator are either all 1s or 0 s , this condition is flagged as a modulator satu ration event. reading chx_err_mod_sat clear s the bit if the error correct s itself. modulator saturation detection can be disable d by clearing the mod_sat_test_en bit. note that the modulator input volta ge is attenuated internally , which means that a modulator output of all 1s or 0s represent s a modulator that is out of bounds and that a reset pulse is required. filter saturation the ad7771 includes digital filte r saturation detection on each - adc channel. this detection indicates that the filter output is out of bounds, which represents an output code approximately 20% higher than positive or negative full scale. reading the chx_err_ filter_sat bit clears the bit if the error corrects itself. the detection can be disable d by cleari ng filter_sat_test_ en bit. output saturation an output saturation event can occur when gain and offset calibration causes the output from the digital filter to clip at either positive or negative full scale. the output does not wrap. reading the chx_err_o utput_sat bit clear s the bit if the error correct s itself. the detection can be disable d by clearing output_sat_ test_en bit. spi transmission errors (spi control mode) all spi errors clear after reading gen_err_reg_1 , which contains the spi errors. these errors are n o t recover ed automatically and , consequently , the alert pin and the alert bit remain set until the error register is read back. crc checksum error if the crc checksum is enable d by setting the spi_crc_ test_en b it, an error bit, spi_crc_ err, is raised if the crc message does not match the message computed by the ad7771 internal crc block. if the crc message does not match the internally computed message, the register is not updated. sclk counter if the number of clocks generated by the co ntroller is not a multiple of 8 after cs is pulled high, an error bit, spi_clk_ count_err is raised . the last co mmand multiple of 8 is executed; however, t he sclk counter can be disable d by setting the spi_clk_count_test_en bit. invalid read when attempting to read back an invalid register address , the spi_invalid_ read_err bit is set. the invalid readback address detection can be disable d by setting the spi_invalid_read_test_en bit. invalid write when attempting to write to an invalid reg ister address , the spi_invalid_write_err bit is set. the invalid write address detection can be disable d by setting the spi_invalid_write_test_en bit. monitoring using the ad7771 sar adc (spi control mode) the ad7771 contains an on - chip sar adc for chip di agnostics, system diagnostics, or measu rement verification. the sar adc has a 12 - bit resolution . the av dd4 and avs s4 pins operate in complete independence of the - adc supplies and , therefore , can be used for chip diagnostics in systems where functional safety is important. the reference for the sar conversion process i s taken from the sar adc supply voltage (avdd4 / avss4) and , therefore , the sar analog input range is from avss4 to avdd4 .
data sheet ad7771 rev. 0 | page 51 of 98 the sar adc has a maximum throughput rate of 256 ksps. the convst _sar pin initiate s a conversion on the sar adc. the maximum allowable frequency of the convst _sar pin is 256 khz. if consecutive conversion s are performed in the sar adc , read back the result from the previous conversion before a new conversion is generate d. o therwise , the results are corrupted . the sar adc is only available in spi control mode. to read conversion results from the sar adc, set the sar_diag_ mode_en bit. after this bit is set, all data shift ed out from the sdo pin originates from the sar adc conversion , as shown in figure 121 . the convst_sar signal can be internally deglitched to avoid false triggers. table 29 . sar synchronization and deglitching convst_deglitch_dis (register 0x 0 13, bits[7:6]) effect on convst_ sar 11 convst_sar goes directly to the sar 10 convst_sar reaches the sar when it is 1 .5 / mclk cycles wide increase t he acquisition time by 1.5/mclk when the deglitch circuitry is enable d . prior to the sar adc, the ad7771 contains an internal multiplexer. this multiplexer can be configured over the spi to set the inputs to the sar adc to be either internal circuit nodes ( in the case of diagnostics ) or to select the external auxain+ and auxain? pins. along with converting external voltages, the sar ad c monitor s the internal nodes on the avdd, iovdd , and dgnd pins, and the dldo and analog ldo ( aldo ) outputs. some voltages are internally attenuated by 6, and the resulting voltage is applied to the sar adc, as shown in table 30. this is useful because variations in the power supply voltage can be monitored. the inpu t multiplexer of the sar is controlled by the global_ mux_config register , and the different inputs available are described in table 30. the sar adc also contains an sar driver amplifier, as shown in figure 122 . this amplifier settle s the sar input to 12 - bit accuracy within the t 33 time. this driver amplifier help s minimize the kick back from the sar converter to the global diagnostic m ux input circu it nodes. use t he auxiliary inputs, auxain+ and auxain? , to validate the - measurements. while operating in spi control mode , the ad7771 ha s three available gpio x ports controlled via the spi . the gpio x pins can be used to control an external , dual 8:1 multiplexer , which , in turn , sample s the eight - c hannels. use t his diagnostic in applications where functional safety is required. this diagnostic aid s in removing the need for a secondary external adc to validate primary measurements on the - channels. temperature sensor the internal die temperature can be measured with an accuracy of 2c. the differential voltage base emitter ( d v be ) is proportional to the temper ature measured referred to 25c. temperature (c) = mv 2 v 6 . 0 ? table 30 . sar mux inputs sar input positive signal negative signal attenuation 6 0 auxa in+ auxain? no 1 d v be avssx no 2 ref1+ ref1? no 3 ref2+ ref2? no 4 ref_out avssx no 5 vcm avssx no 6 areg1cap avssx yes 7 areg2cap avssx yes 8 dregcap dgnd yes 9 avdd1a avssx yes 10 avdd1b avssx yes 11 avdd2a avssx yes 12 avdd2b avssx yes 13 iovdd dgnd yes 14 avdd4 avssx no 15 dgnd avssx yes 16 dgnd avssx yes 17 dgnd avss x yes 18 avdd4 avssx yes 19 ref1 + avssx no 20 ref2+ avssx no 21 avssx avdd4 yes cs sdi sdo 677 15/b865b21b5 5772085675 5772085675 2195621568/75 2195621568/75 13802-121 figure 121 . configuring the ad7771 to operate the spi to read from the sar adc
ad7771 data sheet rev. 0 | page 52 of 98 sar driver control logic fifo on-chip diagnostics spi auxain+ auxainC avdd4 avss4 convst_sar mux deglitch sar adc ref 13802-122 figure 122 . sar adc configuration and control table 31. - diagnostic input voltage recommended voltage reference notes/result 0 floating not applicable not applicable 1 floating not applicable not applicable 2 280 mv differential signal internal/ e xternal pga gain verification 3 external reference , positive/negative external positive full scale 4 external reference , negative/positive external negative full scale 5 external reference , negative/ negative external zero scale 6 internal reference , positive/negative internal positive f ull scale 7 internal reference, negative/positive internal negative full scale 8 internal reference , positive/ positive internal zero scale 9 external reference , positive/ positive external zero scale - adc diagnostics (spi control mode) the ad7771 ? - adc diagnostic functions are accessible through the spi . the internal mux placed before the p ga has different inputs , allowing the user to sel ect a zero - scale , positive full - scale , or negative full - scale input to the ? - adc, which can be converted to verify the correct operation of the ? - adc channel. the diagnostic mux control signals are shared across all the ? - channels. depending on the diagnostic selected , connect the ? - adc reference to a different reference source to guarantee that the conversion is within the measurable range. there are two different wa ys to enable the diagnostic mux , as follows : x setting the chx_rx bit . this bit enable s the input - mux. the multiplexer inputs are described in table 31. the reference used during the conversions are controlled by the ref_mux_ctrl bits . x setting chx_r ef_monitor . this bit has the same effect as enabling the chx_rx bit and select s the vdd1x / avssx supplies as the main reference . if the ainx pin is connected to avssx, the input range is outside the range of avss x + 10 0 mv therefore, results may differ s lightly from the expected value. alternatively, t he inputs can be used to calibrate gain and offset errors.
data sheet ad7771 rev. 0 | page 53 of 98 - ? output data adc conversion outpu t header and data the ad7771 - c onversion results are output on the dout0 to dout3 pins or over the spi , depending on the selected interface. if the doutx interface is selected, the ad7771 acts as the master in the transmission. if the spi is selected, the controller is the master. the drdy signal indicates the end of conversion indepen dent of the interface selected to read back the - conversion . when the spi read s back the - conversion, if a new conversion is completed ( drdy falling edge ) before the previous conversion is read back, the results from previous conversion are overwritten and , consequently , the previous conversion data is corrupted. for each channel , the wi d th is 32 bits long: 8 bits for the header and 24 bits for the - c onversion, as shown in figure 123. 71 1 %,76 %,76 doutx drdy +51 13802-123 figure 123 . adc output 8- bit header plus 24 - bit conversion data in pin control mode, the header is fixed to the crc while in spi mode, and ca n be selected between the crc and error headers. crc header t he crc header is the header generated in pin control mode or in spi control mode if dout_header_format is set. as shown in figure 124 , the header consists of a n alert bit, three bits for the adc channel id , as shown in table 32 , and four bits for the crc. the alert bit is set high if an error is detected in any channe l, as explained in the general errors section. the alert bit remains set to 1 until the error disappears. alert channel number channel number channel number crc crc crc crc 13802-124 figure 124 . crc header table 32 . channel id channel ch_id_2 ch_id_1 ch_id_0 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 the crc generated is eight bit s long; the 4 msbs are placed on the header for the first channel in the pairing and the 4 lsbs on the header of the second channel in the pairing, as shown in table 33. if a channel is disabled, the 24 - bit output data for this channel is 0x000000 . table 33. 8 - bit crc, header configuration (channel 2) ce 0 1 0 crc7 crc6 crc5 crc4 table 34. 8 - bit crc, header configuration (channel 3) ce 0 1 1 crc3 crc2 crc1 crc0 error header (spi control mode) in spi control mode, the default header can be replaced by an er ror header. if the - conversion is read back through the spi , disable the crc by clearing the spi_crc_test_en bit . i f the doutx interface is used , clear the dout_header_ forma t bit. the error header provides information of common error sources specific for each channel , as shown in table 35. modulator and filter errors are indicated even if the checker for these error s are specifically disable d, as described in the - adc errors section . table 35 . status header output bit s name description 7 alert this bit is set high if any of the enabled diagnostic functions have detected an error , including an e xternal clock not detected, a memory map bit flip, or an internal crc error. this bit is n ot channel specific . th is bit clears if the error is no longer present. 6:4 ch_id_ [2:0] thes e bits indicate which adc channel the follo wing conversion data came from ( see table 32). 3 reset_detected this bit indicates if a reset condition occurs . this bit is not channel specific . 2 modulator_ saturate this bit i ndicates that the modulator output is 20 consecutive 0s or 1 s . the bit reset s automatically after the error is no longer present. 1 filter_ saturate this bit indicates that the filter output is out of bounds. the bit reset s automatically after the error is no longer present. 0 ain_ov_uverror this bit indicates that there is an ainx over voltage/under voltage condition on the inputs . this bit is set until the appropriate register is read back and the error is no longer present.
ad7771 data sheet rev. 0 | page 54 of 98 sample rate converte r (src) (spi c o ntrol m o de) the ad7771 impleme nts a patented featured called the src on each - channel that allows the user to configure the output data rate or sampling frequency to any desired value , including non integer values. the src achieves fine resolution contro l over the - adc odr , up to 15.2 sps . in appl ications where the odr must change based on changes in the input signal to maintain sampling coherency , the src provide s fine control over the odr. for example , to achieve the highest classification standard, class a, in power quality applications, coherency must be maintained for 0.01 hz changes in the input power line. use t he src to achieve this sampling frequency accuracy. in pin control mode, the odr is fixed per the predefined pin control options. c onsequently , a noninteger number cannot be selected, as shown in table 13. to set the odr , the user must program up to four registers , depe nding on the decimation value: two registers to program the integer value , n ( the effective decimation rate) , and two registers to program the decimal value, the interpolation factor (if ). th e integer value registers are s r c _n_msb , bits [3:0] and s r c _n_lsb , bits [7:0]. the dec imal part value registers are s r c _if_msb , bits [7:0] and s r c _if_lsb , bits [7:0]. as an example, if an output data rate of 2.8 kh z is required, the decimation rate equates to ? high resolution mode = 2048 / 2.8 = 731.428 ? low power mode = 512/ 2.8 = 182.857 the register values for high resolution mode are as follows: ? 731 ( d ecimal) = 0x2db ? s r c _n_msb , bits [3:0] = 0x02 ? s r c _n_lsb , bits [7:0] = 0xdb ? 0.428 (decimal) = 0.428 2 16 = 28049 (decimal) = 0x6d91 ? s r c _if_msb , bits [7:0] = 0x6d ? s r c _if_lsb , bits [7:0] = 0x91 the src resolution depends on the decimal number used in the decimation, as well as the modulator clock (mod_ m clk), as follows: 16 2 16 2 1 2 3 2 + + = dec dec mod resolution mclk here mod mclk is the modulator frequency. dec is the decimal portion of the decimation rate. in high re solution mode, for a decimal decimation of 450, the resolution is defined as sps 10 2 . 15 2 1 450 3 450 2 2048 6 C 16 2 2 16 = + gpio2 gpio0 gpio0 gpio0 mclk gpio1 gpio2 mclk gpio1 nc gpio2 mclk gpio1 nc ad7771 ad7771 ad7771 61+521721 logic pulse 7//75 61+521721 logic 7//75 61+521721 logic 7//75 mclk 13802-125 figure 125 . hardware odr update
data sheet ad7771 rev. 0 | page 55 of 9 8 src bandwidth the sinc3 and sinc5 filter s architecture allows the user to select a non integer value as the decimation range this versatility means that the filter notches must be adjusted dynamically: two notches (sinc3) or four notches (sinc5) at the variable frequency, and one fixed notch to remove the pga chopping tone. consequently , the traditional formula for the ?0.1 db and ?3 db bandwidth must be adjusted depending on the selected decimation rate. the bandwidth transfer function is not linear but can be approximated by using a linear function. figure 126 to figure 129 s how the correction factor for the ?0.1 db and ?3 db bandwi dth , respectively . in low power mode , the offset must be divided by 4. for example, for sinc5 when the odr = 1000 sps , the ? 0.1 db point is bw = 0.0 377 1000 + 4 355 . 49 = 50.03 hz 7 0 1 2 3 4 5 6 0 100 50 C0.1db frequency (khz) odr (khz) 13802-126 y = 0.049x + 120.41 6 0 1 2 3 4 5 0 100 50 C0.1db frequency (khz) odr (khz) 13802-127 y = 0.0377x + 49.355 40 0 5 10 15 20 25 30 35 0 100 50 C3db frequency (khz) odr (khz) 13802-128 y = 0.2653x + 634.03 30 0 5 10 15 20 25 0 100 50 C3db frequency (khz) odr (khz) 13802-129 y = 0.2053x + 263.94 src group delay the src group delay depends on the selected odr and is de fined by the following equation: src group d elay = odr n src n src pm u _ _ where: pm is a constant equal to 8. src_n is the integer value of the programmed odr. odr is t he programmed output data rate. when using the sinc5 filter, the equation that defines the group delay is src group delay = odr n src n src pm u u _ _ 2 the latency is the contribution of the group delay and the calibration time. latency = group d elay + t cal in high resolution mode, the calibration delay is defined as 62 t mclk , with a maximum error of 2 t mclk . in low power mode, the calibration delay is defined as 121 t mclk , with a maximum error of 4 t mclk . t mclk is the modulator period and is 488 ns in high resolution mode and 1.9 s in low power mode.
ad7771 data sheet rev. 0 | page 56 of 98 settling time the settling time is defined by the contribution of all the internal stages, the filter delay , and the block calibration. when using the sinc3 filter option, t he filter delay is defined as 3/odr. in some extreme cases, such as when an external pulse is applied, this value may increase to 4/odr. if using the sinc5 filter , the filter delay is defined as 5/odr, or 6/odr for extreme cases. data output interface the - output data interface is defined by the conv st _sar , format0 , and format1 pins in pin control mode at power - up. the format x pins cannot be changed dyna mically. table 14 sho ws the available options for pin control mode. if the device is configured in spi control mode, the spi_slave_mode_ en bit enable s the spi to transmit the - adc conversion results, as shown in table 22. dout3 to dout0 data interface stand alone mode in standalone mode , the ad7771 interfa ce acts as a master. there are three different dout configurations, configurable through the format x pins in pin control mode, as shown in figure 130 through figure 132 , or via the dout_format bits , bits [7:6] , in spi control mode, as described in table 36. figure 133, figure 134 , and figure 135 show the expected data outputs for different dout x output modes. table 36. dout x channels dout _format bits / formatx pins number of dout x lines enabled associated channels 00 4 dout0 channel 0 and channel 1 dout1 channel 2 and channel 3 dout2 channel 4 and channel 5 dout3 channel 6 and channel 7 01 2 dout0 channel 0, channel 1, channel 2, and channel 3 dout1 channel 4, channel 5, channel 6, and channel 7 10 or 11 1 dout0 channel 0, channel 1, channel 2, channel 3, channel 4, channel 5, channel 6, and channel 7 dout0 dout1 dout2 dout3 dclk drdy format1 daisy-chaining is not possible in this format format0 ad7771 ch 0 ch 1 ch 0 ch 1 ch 0 ch 1 ch 0 ch 1 13802-130 dgnd dout0: ch 0, ch 1 dout1: ch 2, ch 3 dout2: ch 4, ch 5 dout3: ch 6, ch 7 0 0 00 f 130 . formatx p cft format0 0 format1 0 dout0 dout1 dclk drdy format1 iovdd daisy-chaining is possible in this format dgnd format0 ch 0, ch 1, ch 2, ch 3 output on dout0 ch 4, ch 5, ch 6, ch 7 output on dout1 01 1 0 ad7771 ch 4 ch 5 ch 6 ch 7 ch 0 ch 1 ch 2 ch 3 13802-131 figure 131 . formatx pin configuration format0 = 1, format1 = 0 dout0 dclk drdy format1 iovdd daisy-chaining is possible in this format dgnd format0 ch 0 to ch 7 output on dout0 10 0 1 ad7771 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 13802-132 figure 132 . formatx pin configuration format0 = 0, format1 = 1
data sheet ad7771 rev. 0 | page 57 of 98 ch0-s0 ch1-s0 ch2-s0 ch3-s0 ch0-s1 ch1-s1 ch2-s1 ch3-s1 dclk drdy dout0 sample n sample n + 1 dout1 ch4-s0 ch5-s0 ch6-s0 ch7-s0 ch4-s1 ch5-s1 ch6-s1 ch7-s1 dout0 dout1 13802-133 figure 133 . format 0 = 0, format1 = 0 each dout x outputs two adc conversions (s0 means sample 0 and s1 means sample 1) ch0-s0 ch1-s0 ch2-s0 ch3-s0 ch7-s0 ch4-s0 ch5-s0 ch6-s0 ch0-s1 ch1-s1 ch2-s1 ch3-s1 ch7-s1 ch4-s1 ch5-s1 ch6-s1 dclk drdy dout0 sample n sample n + 1 dout1 dout3 dout2 13802-134 figure 134 . format0 = 0, format1 = 1 channel 0 to channel 3 share dout0, and channel 4 to channel 7 share dout1 (s0 means sample 0 and s1 means sample 1) dclk drdy dout0 sample n sample n + 1 sample n + 2 dout3 dout2 dout1 ch0-s0 ch1-s0 ch2-s0 ch...-s0 ch6-s0 ch7-s0 ch0-s1 ch0-s2 ch0-s3 ch1-s1 ch2-s1 ch...-s1 ch6-s1 ch7-s2 ch1-s2 ch2-s2 ch...-s2 ch6-s2 ch7-s2 13802-135 figure 135 . format0 = 1, format1 = 0 channel 0 to channel 7 output on dout0 only (s0 means sample 0 and s1 means sample 1)
ad7771 data sheet rev. 0 | page 58 of 98 daisy - chain mode daisy - chaining devices allows numerous devices to use the same data interface lines by cascading the outputs of multiple adcs from separate ad7771 devices. in daisy - chain configura - tion , only one device has a direct connection between the dout x interface and the digital host. for the ad7771 , daisy - chain capability is implemented by cascading dout0 and dout1 through a number of devices, or by just using dout0 ( the number of doutx pins available depends on the selected dout x mode ) . the ability to daisy - chain device s and the limit on the number of devices that can be handled by the chain is dependent on the selected dout x mode and the decimation rate employed. when operating in daisy - chain mode, it is required that all ad7771 devices in the ch ain are correctly synchronized. see the digital reset and synchronization pins section for more information. this feature is especially useful for red ucing the component count and wiring connections in , for example, isolated multi converter applications or for systems with a limited interfacing capacity. for daisy - chain operation, there are two different configurations possible , as described in table 37 . using the formatx = 10 mode , dout2 act s as an input pin , as shown in figure 136 . in this case, the dout0 pin of the ad7771 devices is cascaded to the dout2 pin of the next device in the chain. data readback is analogous to clocking a shift register where data is clocked on the rising edge of dclk. table 37. dout x modes in daisy - chain operation dout_format bits / formatx pins number of doutx lines enabled associated channels 01 2 dout0 channel 0 to channel 3 and dout2 dout1 channel 4 to channel 7 and dout3 dout2 input channel dout3 input channel 10 1 dout0 channel 0 to channel 7 and dout2 dout2 i nput c hannel u2 s0 ch0 to ch7 u2 s0 ch0 to ch7 u1 s0 ch0 to ch7 0 0 u2 s0 ch0 to ch7 u1 s0 ch0 to ch7 0 u2 s1 ch0 to ch7 u2 s1 ch0 to ch7 u1 s1 ch0 to ch7 0 0 u2 s1 ch0 to ch7 u2 s3 ch0 to ch7 0 u2 s0 ch0 to ch7 u2 s0 ch0 to ch7 u1 s1 ch0 to ch7 0 u2 dout0 u1 dout2/din0 u1 dout0 u2 dout2/din0 drdy dclk u2 dout2/din0 dout0 u2 dout2/din0 dout0 13802-136 figure 136 . daisy - c hain co nnection mode, format0 = 1 , format1 = 0 (s0 means sample 0 and s1 means sample 1) when connected in daisy - chain mode , dout2 acts as an input pin, represented by din0
data sheet ad7771 rev. 0 | page 59 of 98 minimum dclk x frequency select the dclkx frequency ratio in such a way that the data is completely shifted out befor e a new conversion is completed; otherwise , the previous conversion is overwritten and the tra ns - mission becomes corrupt. the minimum dclkx frequency ratio is defined by the decimation rate , the operation mode , and the lines ena bled on the dout3 to dout0 data interface as described in the following equation s: in standa lone , high resolution mode, dclk min_ ratio < decimation /(8 dout_format ) in standalone, low power mode, dclk min_ratio < decimation /(4 dout_format ) in daisy - chain , high resolution mode, dclk min _ratio < decimation /(8 devices doutx channels ) in daisy - chain, low power mode, dclk min_ratio < decimation /(4 devices doutx channels ) as an example, when operating in master interface mode, formatx = 01, the dout0 and dout1 p ins s hift out four - c hannels each and , assuming a maximum output rate in high resolution mode, the decimation = 128. dclk min < 128/ ( 8 4 ) = 4 if the dclk min_ratio is selected above the necessary minimum, a logic 0 is continuously transmitted until a new sample is available. an example in daisy - chain mode , assuming formatx = 01, and with t hree devices connected and a decimation rate of 256 in high resolution mode , is as follows: dclk min_ratio < 256/( 8 3 4 ) = 2.66 = 2 the different ratios are summarized in table 38. table 38. available dclk ratios dclk_clk_div (spi control mode), dclkx (pin control mode) dclk x ratio 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 there are maximum achievable odrs and minimum dclk x frequencies required for a given dout x pin configuration , as shown in table 39 and table 40 . table 39 . maximum odrs and minimum dclk x frequencies in high resolution mode decimation rate odr (ksps) minimum dclk x (khz) 1 1 dout x 2 dout x 4 dout x 4095 0.500122 128 64 32 2048 1 256 128 64 1024 2 512 256 128 512 4 1024 512 256 256 8 2048 1024 512 128 16 4096 2048 1024 64 32 8192 4096 2048 32 64 n/a 8192 4096 16 128 n/a n/a 8192 1 n/a means not applicable. table 40 . maximum odrs and minimum dclk frequencies in low power mode decimation rate odr (ksps) minimum dclk x (khz) 1 doutx 2 doutx 4 doutx 2048 0.25 64 32 16 1024 0.5 128 64 32 512 1 256 128 64 256 2 512 256 128 128 4 1024 512 256 64 8 2048 1024 512 32 16 4096 2048 1024 16 32 n/a 1 4096 2048 1 n/a means not applicable. if the ad7771 operates in spi control mode, it is possible to adjust the doutx strength, which can be selected in the dout_drive_str bits, as described in table 41. table 41 . doutx strength dout_drive_str mode 00 nominal 01 strong 10 weak 11 extra strong spi the spi gives the user flexibility to read the conversion from the - adc where the processor or micro controller is the master. when a new conversion is completed, the drdy signal is toggled to indicate that data can be accessed. when drdy t oggles, the internal channel counter is reset and the next spi read originates from channel 0 again. conversely, after the last channel data is read , all succ e ssive reads before the next drdy signal originate f rom ch annel 7 ( lsb ).
ad7771 data sheet rev. 0 | page 60 of 98 ch0_header _+_ch0_8_bits_msb ch0_16_bits_lsb 13802-137 cs sdo figure 137 . spi readback, 16 bits per frame cs sdo ch0_header _+_ch0_16_bits_msb ch0_8_bits_lsb_+_ch1_header_+ch1_8_bits_msb 13802-138 figure 138 . spi readback, 24 bits per frame the spi operates in multiples of 8 bits per frame; figure 137 shows a readback example in 16 bits per frames, and figure 138 shows a readba c k in 24 bits per frame. note that i f the device is configured in spi control mode, the ad7771 generate s a software reset if the sdi pin is sample d high for 64 consecutive clocks. to avoid a reset or unwanted register writes, it is recommended to transfer a 0x8000 command, which generates a readback command that is ignored by the device, as explained in the spi software reset section . calculating the crc check s um the ad7771 implements two different crc checksum generators, one for the - results and another for the spi control mode. the ad7771 uses a crc polynom i al to calculate the crc checks um value. the 8 - bit crc polynomial used is x 8 + x 2 + x + 1. the polynomial is aligned so that its msb is adjacent to the leftmost logic 1 of the data. an exclusive or (xor ) function is applied to the data to produce a new, sh orter number. the polynomial is again aligned so that its msb is adjacent to the leftmost logic 1 of the new result, and the procedure is repeated. this process is repeated until the original data is reduced to a value less than the polynomial. this is the 8 - bit checksum. a n example of crc ca lculation for 12 - bit data is shown in table 42. table 42 . example crc calculation for 12 - bit data 1 data 0 1 1 0 0 1 0 0 1 1 1 0 polynomial 1 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 1 0 0 0 0 0 1 1 crc 0 1 0 1 1 1 1 0 1 this table represents the division of the data; blank cells are for formatting purposes. ? - ? crc checksum the crc message is calculated internally by the ad7771 on adc pairs. the crc is calculated using t he adc output data from two adc s and bits[ 7:4 ] from the header. therefore, 56 bit s are used to calculate the 8 - bit crc. this crc is split between the two channel headers. the crc data cover s channel pairings as follows : channel 0 and channel 1, channel 2 and channel 3, channel 4 and channel 5, and channel 6 and channel 7. to generate t he checksum, the data is left shifted by eight bits to create a number ending in eight logic 1s. the crc is calculated from 56 bits across two consecutive/ channel pairings (channel 0 and ch annel 1, channel 2 and channel 3, channel 4 and channel 5, channel 6 , and channel 7) . the 56 bits consist of the alert bit , the 3 bits for the first adc pairing channel , and the 24 bits of data of each pairing channel. for example , for the second channel pairing, channel 2 and channel 3 , 56 bits = alert bit + 3 adc channel bits (010) + 24 data bit s (channel 2 ) + alert bit + 3 adc channel bits (011) + 24 data bits (channel 3) spi control mode checksum the crc message is calculated internally by the ad7771 . the dat a transferred to the ad7771 uses the r /w bit, a 7 - bit address , and 8 bits of data for the crc calculation. the crc calculated and appended to the data that is shift ed out uses a 0010 0000 header and 8 bits of data for the register readback, as well as the 0010 header and 12 bits of sar conversio n data for th e sar readback transfers.
data sheet ad7771 rev. 0 | page 61 of 98 register summary table 43 . register summary reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x000 ch0_config [7:0] ch0_gain ch0_ref_ monitor ch0_rx reserved 0x00 /w r 0x001 ch1_config [7:0] ch1_gain ch1_ref_ monitor ch1_rx reserved 0x00 r/w 0x002 ch2_config [7:0] ch2_gain ch2_ref_ monitor ch2_rx reserved 0x00 r/w 0x003 ch3_config [7:0] ch3_gain ch3_ref_ monitor ch3_rx reserved 0x00 r/w 0x004 ch4_config [7:0] ch4_gain ch4_ref_ monitor ch4_rx reserved 0x00 r/w 0x005 ch5_config [7:0] ch5_gain ch5_ref_ monitor ch5_rx reserved 0x00 r/w 0x006 ch6_config [7:0] ch6_gain ch6_ref_ monitor ch6_rx reserved 0x00 r/w 0x007 ch7_config [7:0] ch7_gain ch7_ref_ monitor ch7_rx reserved 0x00 r/w 0x008 ch_disable [7:0] ch7_ disable ch6_ disable ch5_disable ch4_ disable ch3_ disable ch2_ disable ch1_ disable ch0_ disable 0x00 r/w 0x009 ch0_sync_ offset [7:0] ch0_sync_offset 0x00 r/w 0x00a ch1_sync_ offset [7:0] ch1_sync_offset 0x00 r/w 0x00b ch2_sync_ offset [7:0] ch2_sync_offset 0x00 r/w 0x00c ch3_sync_ offset [7:0] ch3_sync_offset 0x00 r/w 0x00d ch4_sync_ offset [7:0] ch4_sync_offset 0x00 r/w 0x00e ch5_sync_ offset [7:0] ch5_sync_offset 0x00 r/w 0x00f ch6_sync_ offset [7:0] ch6_sync_offset 0x00 r/w 0x010 ch7_sync_ offset [7:0] ch7_sync_offset 0x00 r/w 0x011 general_ user_ config_1 [7:0] all_ ch_dis_ mclk_en power - mode pdb_vcm pdb_ refout_buf pdb_ sar pdb_ rc_osc soft_reset 0x24 r/w 0x012 general_ user_ config_2 [7:0] reserved filter_ mode sar_diag_ mode_en sdo_drive_str dout_drive_str spi_sync 0x09 r/w 0x013 general_ user_ config_3 [7:0] convst_ deglitch_dis reserved spi_slave_ mode_en reserved clk_ qual_dis 0x80 r/w 0x014 dout_format [7:0] dout_format dout_ header_ format reserved dclk_clk_div reserved 0x20 r/w 0x015 adc_mux_ config [7:0] ref_mux_ctrl mtr_mux_ctrl reserved 0x00 r/w 0x016 global_mux_ config [7:0] global_mux_ctrl reserved 0x00 r/w 0x017 gpio_config [7:0] reserved gpio_op_en 0x00 r/w 0x018 gpio_data [7:0] reserved gpio_read_data gpio_write_data 0x00 r/w 0x019 buffer_ config_1 [7:0] reserved ref_buf_ pos_en ref_ buf_ neg_en reserved 0x38 r/w 0x01a buffer_ config_2 [7:0] ref - bufp_ preq ref - bufn_ preq reserved pdb_ aldo1_ovr drv pdb_ aldo2_ ovrdrv pdb_ dldo_ ovrdrv 0xc0 r/w 0x01c ch0_offset_ upper_byte [7:0] ch0_offset_all[23:16] 0x00 r/w 0x01d ch0_offset_ mid_byte [7:0] ch0_offset_all[15:8] 0x00 r/w
ad7771 data sheet rev. 0 | page 62 of 98 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x01e ch0_offset_ lower_byte [7:0] ch0_offset_all[7:0] 0x00 r/w 0x01f ch0_gain_ upper_byte [7:0] ch0_gain_ all[23:16] 0x00 r/w 0x020 ch0_gain_ mid_byte [7:0] ch0_gain _ all[15:8] 0x00 r/w 0x021 ch0_gain_ lower_byte [7:0] ch0_gain _ all[7:0] 0x00 r/w 0x022 ch1_offset_ upper_byte [7:0] ch1_offset_all[23:16] 0x00 r/w 0x023 ch1_offset_ mid_byte [7:0] ch1_offset_all[15:8] 0x00 r/w 0x024 ch1_offset_ lower_byte [7:0] ch1_offset_all[7:0] 0x00 r/w 0x025 ch1_gain_ upper_byte [7:0] ch1_gain _ all[23:16] 0x00 r/w 0x026 ch1_gain_ mid_byte [7:0] ch1_gain _ all[15:8] 0x00 r/w 0x027 ch1_gain_ lower_byte [7:0] ch1_gain _ all[7:0] 0x00 r/w 0x028 ch2_offset_ upper_byte [7:0] ch2_offset_all[23:16] 0x00 r/w 0x029 ch2_offset_ mid_byte [7:0] ch2_offset_all[15:8] 0x00 r/w 0x02a ch2_offset_ lower_byte [7:0] ch2_offset_all[7:0] 0x00 r/w 0x02b ch2_gain_ upper_byte [7:0] ch2_gain _ all[23:16] 0x00 r/w 0x02c ch2_gain_ mid_byte [7:0] ch2_gain _ all[15:8] 0x00 r/w 0x02d ch2_gain_ lower_byte [7:0] ch2_gain _ all[7:0] 0x00 r/w 0x02e ch3_offset_ upper_byte [7:0] ch3_offset_all[23:16] 0x00 r/w 0x02f ch3_offset_ mid_byte [7:0] ch3_offset_all[15:8] 0x00 r/w 0x030 ch3_offset_ lower_byte [7:0] ch3_offset_all[7:0] 0x00 r/w 0x031 ch3_gain_ upper_byte [7:0] ch3_gain _ all[23:16] 0x00 r/w 0x032 ch3_gain_ mid_byte [7:0] ch3_gain _ all[15:8] 0x00 r/w 0x033 ch3_gain_ lower_byte [7:0] ch3_gain _ all[7:0] 0x00 r/w 0x034 ch4_offset_ upper_byte [7:0] ch4_offset_all[23:16] 0x00 r/w 0x035 ch4_offset_ mid_byte [7:0] ch4_offset_all[15:8] 0x00 r/w 0x036 ch4_offset_ lower_byte [7:0] ch4_offset_all[7:0] 0x00 r/w 0x037 ch4_gain_ upper_byte [7:0] ch4_gain _ all[23:16] 0x00 r/w 0x038 ch4_gain_ mid_byte [7:0] ch4_gain _ all[15:8] 0x00 r/w 0x039 ch4_gain_ lower_byte [7:0] ch4_gain _ all[7:0] 0x00 r/w 0x03a ch5_offset_ upper_byte [7:0] ch5_offset_all[23:16] 0x00 r/w 0x03b ch5_offset_ mid_byte [7:0] ch5_offset_all[15:8] 0x00 r/w 0x03c ch5_offset_ lower_byte [7:0] ch5_offset_all[7:0] 0x00 r/w 0x03d ch5_gain_ upper_byte [7:0] ch5_gain _ all[23:16] 0x00 r/w 0x03e ch5_gain_ mid_byte [7:0] ch5_gain _ all[15:8] 0x00 r/w
data sheet ad7771 rev. 0 | page 63 of 98 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x03f ch5_gain_ lower_byte [7:0] ch5_gain _ all[7:0] 0x00 r/w 0x040 ch6_offset_ upper_byte [7:0] ch6_offset_all[23:16] 0x00 r/w 0x041 ch6_offset_ mid_byte [7:0] ch6_offset_all[15:8] 0x00 r/w 0x042 ch6_offset_ lower_byte [7:0] ch6_offset_all[7:0] 0x00 r/w 0x043 ch6_gain_ upper_byte [7:0] ch6_gain _ all[23:16] 0x00 r/w 0x044 ch6_gain_ mid_byte [7:0] ch6_gain _ all[15:8] 0x00 r/w 0x045 ch6_gain_ lower_byte [7:0] ch6_gain _ all[7:0] 0x00 r/w 0x046 ch7_offset_ upper_byte [7:0] ch7_offset_all[23:16] 0x00 r/w 0x047 ch7_offset_ mid_byte [7:0] ch7_offset_all[15:8] 0x00 r/w 0x048 ch7_offset_ lower_byte [7:0] ch7_offset_all[7:0] 0x00 r/w 0x049 ch7_gain_ upper_byte [7:0] ch7_gain _ all[23:16] 0x00 r/w 0x04a ch7_gain_ mid_byte [7:0] ch7_gain _ all[15:8] 0x00 r/w 0x04b ch7_gain_ lower_byte [7:0] ch7_gain _ all[7:0] 0x00 r/w 0x04c ch0_err_reg [7:0] reserved ch0_err_ ainm_uv ch0_err_ ainm_ov ch0_err_ ainp_uv ch0_err_ ainp_ov ch0_err_ ref_det 0x00 r 0x04d ch1_err_reg [7:0] reserved ch1_err_ ainm_uv ch1_err_ ainm_ov ch1_err_ ainp_uv ch1_err_ ainp_ov ch1_err_ ref_det 0x00 r 0x04e ch2_err_reg [7:0] reserved ch2_err_ ainm_uv ch2_err_ ainm_ov ch2_err_ ainp_uv ch2_err_ ainp_ov ch2_err_ ref_det 0x00 r 0x04f ch3_err_reg [7:0] reserved ch3_err_ ainm_uv ch3_err_ ainm_ov ch3_err_ ainp_uv ch3_err_ ainp_ov ch3_err_ ref_det 0x00 r 0x050 ch4_err_reg [7:0] reserved ch4_err_ ainm_uv ch4_err_ ainm_ov ch4_err_ ainp_uv ch4_err_ai np_ov ch4_err_ ref_det 0x00 r 0x051 ch5_err_reg [7:0] reserved ch5_err_ ainm_uv ch5_err_ ainm_ov ch5_err_ ainp_uv ch5_err_ ainp_ov ch5_err_ ref_det 0x00 r 0x052 ch6_err_reg [7:0] reserved ch6_err_ ainm_uv ch6_err_ ainm_ov ch6_err_ ainp_uv ch6_err_ ainp_ov ch6_err_ ref_det 0x00 r 0x053 ch7_err_reg [7:0] reserved ch7_err_ ainm_uv ch7_err_ ainm_ov ch7_err_ ainp_uv ch7_err_ ainp_ov ch7_err_ ref_det 0x00 r 0x054 ch0_1_sat_ err [7:0] reserved ch1_err_ mod_sat ch1_err_ filter_sat ch1_err_ output_ sat ch0_err_ mod_sat ch0_err_ filter_sat ch0_err_ output_ sat 0x00 r 0x055 ch2_3_sat_ err [7:0] reserved ch3_err_ mod_sat ch3_err_ filter_sat ch3_err_ output_ sat ch2_err_ mod_sat ch2_err_ filter_sat ch2_err_ output_ sat 0x00 r 0x056 ch4_5_sat_ err [7:0] reserved ch5_err_ mod_sat ch5_err_ filter_sat ch5_err_ output_ sat ch4_err_ mod_sat ch4_err_ filter_sat ch4_err_ output_ sat 0x00 r 0x057 ch6_7_sat_ err [7:0] reserved ch7_err_ mod_sat ch7_err_ filter_sat ch7_err_ output_ sat ch6_err_ mod_sat ch6_err_ filter_sat ch6_err_ output_ sat 0x00 r 0x058 chx_err_ reg_en [7:0] output_ sat_ test_en filter_ sat_ test_en mod_sat_ test_en ainm_uv_ test_en ainm_ov_ test_en ainp_uv_ test_en ainp_ov_ test_en ref_det_ test_en 0xfe r/w 0x059 gen_err_ reg_1 [7:0] reserved memmap_ crc_err rom_crc_ err spi_clk_ count_ err spi_ invalid_ read_err spi_ invalid_ write_err spi_crc_ err 0x00 r 0x05a gen_err_ reg_1_en [7:0] reserved memmap_ crc_test_en rom_crc_ test_en spi_clk_ count_ test_en spi_ invalid_ read_ test_en spi_ invalid_ write_ test_en spi_crc_ test_ en 0x3e r/w 0x05b gen_err_ reg_2 [7:0] reserved reset_ detected ext_mclk_ switch_err reserved aldo1_ psm_err aldo2_ psm_err dldo_ psm_err 0x00 r 0x05c gen_err_ reg_2_en [7:0] reserved reset_ detect_en reserved ldo_psm_test_ en ldo_psm_trip_test_en 0x3c r/w
ad7771 data sheet rev. 0 | page 64 of 98 reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r/w 0x05d status_reg_1 [7:0] reserved chip_error err_loc_ ch4 err_loc_ ch3 err_loc_ ch2 err_loc_ ch1 err_loc_c h0 0x00 r 0x05e status_reg_2 [7:0] reserved chip_error err_loc_ gen2 err_loc_ gen1 err_loc_ ch7 err_loc_ ch6 err_loc_c h5 0x00 r 0x05f status_reg_3 [7:0] reserved chip_error init_ complete err_loc_ sat_ch6_ 7 err_loc_ sat_ch4_5 err_loc_ sat_ch2_3 err_loc_ sat_ch0_1 0x00 r 0x060 src_n_msb [7:0] reserved src_n_all[11:8] 0x00 r/w 0x061 src_n_lsb [7:0] src_n_all[7:0] 0x80 r/w 0x062 src_if_msb [7:0] src_if_all[15:8] 0x00 r/w 0x063 src_if_lsb [7:0] src_if_all[7:0] 0x00 r/w 0x064 src_update [7:0] src_ load_ source reserved src_load_ update 0x00 r/w
data sheet ad7771 rev. 0 | page 65 of 98 register details channel 0 configuration register address: 0x000, reset: 0x00, name: ch0_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch0_gain (r/w) [2:0] reserved [5] ch0_ref_monitor (r/w ) [3] reserved [4] ch0_rx (r/w) table 44. bit descriptions for ch0_config bits bit name settings description reset access [7:6] ch0_gain afe gain 0x0 r/w 00 gain = 1 01 gain = 2 10 gain = 4 11 gain = 8 5 ch0_ref_monitor channel used as reference monitor 0x0 r/w 4 ch0_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w channel 1 configuration register address: 0x001, reset: 0x00, name: ch1_config a fe gain 11: gain = 8. 10: gain = 4. 01: gain = 2. 00: gain = 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch1_gain (r/w) [2:0] reserved [5] ch1_ref_monitor (r/w) [3] reserved [4] ch1_rx (r/w) table 45. bit descriptions for ch1_config bits bit name settings description reset access [7:6] ch1_gain afe gain 0x0 r/w 00 gain = 1 01 gain = 2 10 gain = 4 11 gain = 8 5 ch1_ref_monitor channel used as reference monitor 0x0 r/w 4 ch1_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w
ad7771 data sheet rev. 0 | page 66 of 98 channel 2 configuration register address: 0x002, reset: 0x00, name: ch2_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch2_gain (r/w) [2:0] reserved [5] ch2_ref_monitor (r/w) [3] reserved [4] ch2_rx (r/w) table 46. bit descriptions for ch2_config bits bit name settings description reset access [7:6] ch2_gain afe gain 0x0 r/w 00 gain = 1 01 gain = 2 10 gain = 4 11 gain = 8 5 ch2_ref_monitor channel used as reference monitor 0x0 r/w 4 ch2_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w channel 3 configuration register address: 0x003, reset: 0x00, name: ch3_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch3_gain (r/w) [2:0] reserved [5] ch3_ref_monitor (r/w) [3] reserved [4] ch3_rx (r/w) table 47. bit descriptions for ch3_config bits bit name settings description reset access [7:6] ch3_gain afe gain 0x0 r/w 00 gain = 1 01 gain = 2 10 gain = 4 11 gain = 8 5 ch3_ref_monitor channel used as reference monitor 0x0 r/w 4 ch3_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w
data sheet ad7771 rev. 0 | page 67 of 98 channel 4 configuration register address: 0x004, reset: 0x00, name: ch4_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch4_gain (r/w) [2:0] reserved [5] ch4_ref_monitor (r/w) [3] reserved [4] ch4_rx (r/w) table 48. bit descriptions for ch4_config bits bit name settings description reset access [7:6] ch4_gain afe gain 0x0 r/w 00 gain = 1 01 gain = 2 10 gain = 4 11 gain = 8 5 ch4_ref_monitor channel used as reference monitor 0x0 r/w 4 ch4_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w channel 5 configuration register address: 0x005, reset: 0x00, name: ch5_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch5_gain (r/w) [2:0] reserved [5] ch5_ref_monitor (r/w) [3] reserved [4] ch5_rx (r/w) table 49. bit descriptions for ch5_config bits bit name settings description reset access [7:6] ch5_gain afe gain 0x0 r/w 00 gain = 1 01 gain = 2 10 gain = 4 11 gain = 8 5 ch5_ref_monitor channel used as reference monitor 0x0 r/w 4 ch5_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w
ad7771 data sheet rev. 0 | page 68 of 98 channel 6 configuration register address: 0x006, reset: 0x00, name: ch6_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch6_gain (r/w) [2:0] reserved [5] ch6_ref_monitor (r/w) [3] reserved [4] ch6_rx (r/w) table 50. bit descriptions for ch6_config bits bit name settings description reset access [7:6] ch6_gain afe gain 0x0 r/w 00 gain = 1 01 gain = 2 10 gain = 4 11 gain = 8 5 ch6_ref_monitor channel used as reference monitor 0x0 r/w 4 ch6_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w channel 7 configuration register address: 0x007, reset: 0x00, name: ch7_config a fe gain 11: gain 8. 10: gain 4. 01: gain 2. 00: gain 1. channel used as reference monitor channel meter mux rx mode 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ch7_gain (r/w) [2:0] reserved [5] ch7_ref_monitor (r/w) [3] reserved [4] ch7_rx (r/w) table 51. bit descriptions for ch7_config bits bit name settings description reset access [7:6] ch7_gain afe gain 0x0 r/w 00 gain = 1 01 gain = 2 10 gain = 4 11 gain = 8 5 ch7_ref_monitor channel used as reference monitor 0x0 r/w 4 ch7_rx channel meter mux rx mode 0x0 r/w [3:0] reserved reserved 0x0 r/w
data sheet ad7771 rev. 0 | page 69 of 98 disable clocks to adc channel register address: 0x008, reset: 0x00, name: ch_disable channel 7 disable channel 0 disable channel 6 disable channel 1 disable channel 5 disable channel 2 disable channel 4 disable channel 3 disable 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7] ch7_disable (r/w ) [0] ch0_disable (r/w ) [6] ch6_disable (r/w ) [1] ch1_disable (r/w ) [5] ch5_disable (r/w ) [2] ch2_disable (r/w ) [4] ch4_disable (r/w ) [3] ch3_disable (r/w ) table 52. bit descriptions for ch_disable bits bit name settings description reset access 7 ch7_disable channel 7 disable 0x0 r/w 6 ch6_disable channel 6 disable 0x0 r/w 5 ch5_disable channel 5 disable 0x0 r/w 4 ch4_disable channel 4 disable 0x0 r/w 3 ch3_disable channel 3 disable 0x0 r/w 2 ch2_disable channel 2 disable 0x0 r/w 1 ch1_disable channel 1 disable 0x0 r/w 0 ch0_disable channel 0 disable 0x0 r/w channel 0 sync offset register address: 0x009, reset: 0x00, name: ch0_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_sync_offset (r/w ) table 53. bit descriptions for ch0_sync_offset bits bit name settings description reset access [7:0] ch0_sync_offset channel sync offset 0x0 r/w channel 1 sync offset register address: 0x00a, reset: 0x00, name: ch1_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_sync_offset (r/w ) table 54. bit descriptions for ch1_sync_offset bits bit name settings description reset access [7:0] ch1_sync_offset channel sync offset 0x0 r/w channel 2 sync offset register address: 0x00b, reset: 0x00, name: ch2_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_sync_offset (r/w ) table 55. bit descriptions for ch2_sync_offset bits bit name settings description reset access [7:0] ch2_sync_offset channel sync offset 0x0 r/w
ad7771 data sheet rev. 0 | page 70 of 98 channel 3 sync offset register address: 0x00c, reset: 0x00, name: ch3_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_sync_offset (r/w ) table 56. bit descriptions for ch3_sync_offset bits bit name settings description reset access [7:0] ch3_sync_offset channel sync offset 0x0 r/w channel 4 sync offset register address: 0x00d, reset: 0x00, name: ch4_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_sync_offset (r/w ) table 57. bit descriptions for ch4_sync_offset bits bit name settings description reset access [7:0] ch4_sync_offset channel sync offset 0x0 r/w channel 5 sync offset register address: 0x00e, reset: 0x00, name: ch5_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_sync_offset (r/w ) table 58. bit descriptions for ch5_sync_offset bits bit name settings description reset access [7:0] ch5_sync_offset channel sync offset 0x0 r/w channel 6 sync offset register address: 0x00f, reset: 0x00, name: ch6_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_sync_offset (r/w ) table 59. bit descriptions for ch6_sync_offset bits bit name settings description reset access [7:0] ch6_sync_offset channel sync offset 0x0 r/w channel 7 sync offset register address: 0x010, reset: 0x00, name: ch7_sync_offset channel sync offset 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_sync_offset (r/w ) table 60. bit descriptions for ch7_sync_offset bits bit name settings description reset access [7:0] ch7_sync_offset channel sync offset 0x0 r/w
data sheet ad7771 rev. 0 | page 71 of 98 general user configuration 1 register address: 0x011, reset: 0x24, name: general_user_config_1 if all sd channels are disabled, setting this bit high allows dclk to continue toggling soft res et 11: 1st write. 10: 2nd write. 01: no effect. 00: no effect. power mode 1: high resolution. 0: low power (1/4) power-down signal for internal oscillator . active low power-down vcm buffer. active low power-down sar. active low power-down internal reference output buffer. active low 0 0 1 0 2 1 3 0 4 0 5 1 6 0 7 0 [7] all_ch_dis_mclk_en (r/w) [1:0] soft_reset (r/w) [6] powermode (r/w) [2] pdb_rc_osc (r/w) [5] pdb_vcm (r/w) [3] pdb_sar (r/w) [4] pdb_refout_buf (r/w ) table 61. bit descriptions for general_user_config_1 bits bit name settings description reset access 7 all_ch_dis_mclk_en if all - channels are disabled, setting this bit high allows dclk to continue toggling. 0x0 r/w 6 powermode power mode. 0x0 r/w 0 low power (1/4). 1 high resolution. 5 pdb_vcm power-down vcm buffer. active low. 0x1 r/w 4 pdb_refout_buf power-down internal refe rence output buffer. active low. 0x0 r/w 3 pdb_sar power-down sar. active low. 0x0 r/w 2 pdb_rc_osc power-down signal for internal oscillator. active low. 0x1 r/w [1:0] soft_reset soft reset 0x0 r/w 00 no effect 01 no effect 10 2nd write 11 1st write
ad7771 data sheet rev. 0 | page 72 of 98 general user configuration 2 register address: 0x012, reset: 0x09, name: general_user_config_2 sync pulse generated thru spi 1: startb pin in the control module. this bit is anded with the value on 0: generate a pulse in /sync_in pin. on startb pin in the control module , this signal is anded with the value 0=sinc3. 1=sinc5 dout drive strength 11: extra strong. 10: weak. 01: strong. 00: nominal. sets spi interface to read back sar result on sdo sdo drive strength 11: extra strong. 10: weak. 01: strong. 00: nominal. 0 1 1 0 2 0 3 1 4 0 5 0 6 0 7 0 [7] reserved [0] spi_sync (r/w) [6] filter_mode (r/w) [2:1] dout_drive_str (r/w ) [5] sar_diag_mode_en (r/w) [4:3] sdo_drive_str (r/w) table 62. bit descriptions for general_user_config_2 bits bit name settings description reset access 7 reserved reserved. 0x0 r/w 6 filter_mode 0 = sinc3. 1 = sinc5. 0x0 r/w 5 sar_diag_mode_en sets spi interface to read back sar result on sdo. 0x0 r/w [4:3] sdo_drive_str sdo drive strength. 0x1 r/w 00 nominal. 01 strong. 10 weak. 11 extra strong. [2:1] dout_drive_str doutx drive strength. 0x0 r/w 00 nominal. 01 strong. 10 weak. 11 extra strong. 0 spi_sync sync pulse generated through spi. 0x1 r/w 0 this signal is anded with the value on start pin in the control module to generate a pulse in sync_in pin. 1 this bit is anded with the value on start pin in the control module.
data sheet ad7771 rev. 0 | page 73 of 98 general user configuration 3 register address: 0x013, reset: 0x80, name: general_user_config_3 disable deglitching of convst_sar pin 11: no deglitch circuit. 10: convst_sar deglitch 1.5/ mclk. 01: reserved. 00: reserved. disables the clock qualifier check if the user requires to use an mclk signal < 265khz. enable to spi slave mode to read back adc on sdo 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 [7:6] convst_deglitch_dis (r/w ) [0] clk_qual_dis (r/w ) [5] reserved [3:1] reserved [4] spi_slave_mode_en (r/w) table 63. bit descriptions for general_user_config_3 bits bit name settings description reset access [7:6] convst_deglitch_dis disable deglitching of convst_sar pin. 0x2 r/w 00 reserved. 01 reserved. 10 convst_sar deglitch 1.5/mclk. 11 no deglitch circuit. 5 reserved reserved. 0x0 r/w 4 spi_slave_mode_en enable to spi slave mode to read back adc on sdo. 0x0 r/w [3:2] reserved reserved. 0x0 r/w 1 reserved reserved. 0x0 r/w 0 clk_qual_dis disables the clock qualifier check if the user requires to use an mclk signal <265 khz. 0x0 r/w data output format register address: 0x014, reset: 0x20, name: dout_format data out form at 11: 1 dout lines. 10: 1 dout lines. 01: 2 dout lines. 00: 4 dout lines. dout header format 1: crc header. 0: status header. divide mclk 111: divide by 128. 110: divide by 64. 101: divide by 32. 100: divide by 16. 011: divide by 8. 010: divide by 4. 001: divide by 2. 000: divide by 1. 0 0 1 0 2 0 3 0 4 0 5 1 6 0 7 0 [7:6] dout_format (r/w ) [0] reserved [5] dout_header_format (r/w ) [3:1] dclk_clk_div (r/w ) [4] reserved table 64. bit descriptions for dout_format bits bit name settings description reset access [7:6] dout_format data out format 0x0 r/w 00 4 doutx lines 01 2 doutx lines 10 1 doutx lines 11 1 doutx line 5 dout_header_format doutx header format 0x1 r/w 0 status header 1 crc header 4 reserved reserved 0x0 r/w
ad7771 data sheet rev. 0 | page 74 of 98 bits bit name settings description reset access [3:1] dclk_clk_div divide mclk 0x0 r/w 000 divide by 1 001 divide by 2 010 divide by 4 011 divide by 8 100 divide by 16 101 divide by 32 110 divide by 64 111 divide by 128 0 reserved reserved 0x0 r/w main adc meter and reference mux control register address: 0x015, reset: 0x00, name: adc_mux_config sd adc reference mux 11: external reference refx-/refx+. 10: external supply avdd1x/avssx. 01: internal reference. 00: external reference refx+/refx- sd ad c mete r mux 1001: external reference refx+/refx+. 1000: internal reference +/+. 0111: internal reference -/+. 0110: internal reference +/- 0101: external reference refx-/refx- 0100: external reference refx-/refx+. 0011: external reference refx+/refx- 0010: 280mv. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] ref_mux_ctrl (r/w ) [1:0] reserved [5:2] mtr_mux_ctrl (r/w ) table 65. bit descriptions for adc_mux_config bits bit name settings description reset access [7:6] ref_mux_ctrl - adc reference mux. 0x0 r/w 00 external reference refx+/refx?. 01 internal reference. 10 external supply avdd1x/avssx. 11 external reference refx?/refx+. [5:2] mtr_mux_ctrl - adc meter mux. 0x0 r/w 0010 280 mv. 0011 external reference refx+/refx?. 0100 external reference refx?/refx+. 0101 external reference refx?/refx?. 0110 internal reference +/?. 0111 internal reference ?/+. 1000 internal reference +/+. 1001 external reference refx+/refx+. [1:0] reserved reserved. 0x0 r/w
data sheet ad7771 rev. 0 | page 75 of 98 global diagnostics mux register address: 0x016, reset: 0x00, name: global_mux_config global sar diagnostics mux control 10101: avssx avdd4. attenuated. 10100: ref2+ avssx. 10011: ref1+ avssx. ... 00010: ref1p ref1n. 00001: dvbe avssx. 00000: auxain+ auxain- 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:3] global_mux_ctrl (r/w ) [2:0] reserved table 66. bit descriptions for global_mux_config bits bit name settings description reset access [7:3] global_mux_ctrl global sar diagnostics mux control. 0x0 r/w 00000 auxain+/auxain?. 00001 dv be /avssx. 00010 ref1+/ref1?. 10011 ref2+/ref2?. 10100 ref_out/avssx. 10101 vcm/avssx. 10110 areg1cap/avssx. 10111 areg2cap/avssx. 11000 dregcap/dgnd. 11001 avdd1a/avssx. 11010 avdd1b/avssx. 11011 avdd2a/avssx. 11100 avdd2b/avssx. 11101 iovdd/dgnd. 11110 avdd4/avssx. 11111 dgnd/avssx. 10000 dgnd/avssx. 10001 dgnd/avssx. 10010 avdd4/avssx. 10011 ref1+/avssx. 10100 ref2+/avssx. 10101 avssx/avdd4. attenuated. [2:0] reserved reserved. 0x0 r/w gpio configuration register address: 0x017, reset: 0x00, name: gpio_config gpio input/output 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:3] reserved [2:0] gpio_op_en (r/w) table 67. bit descriptions for gpio_config bits bit name settings description reset access [7:3] reserved reserved. 0x0 r/w [2:0] gpio_op_en gpio input/output 0x0 r/w
ad7771 data sheet rev. 0 | page 76 of 98 gpio data register address: 0x018, reset: 0x00, name: gpio_data value sent to gpio pins data read from gpio pins 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [2:0] gpio_write_data (r/w ) [5:3] gpio_read_data (r) table 68. bit descriptions for gpio_data bits bit name settings description reset access [7:6] reserved reserved. 0x0 r/w [5:3] gpio_read_data data read from the gpio pins 0x0 r [2:0] gpio_write_data value sent to the gpio pins 0x0 r/w buffer configuration 1 register address: 0x019, reset: 0x38, name: buffer_config_1 reference buffer positive enable reference buffer negative enable 0 0 1 0 2 0 3 1 4 1 5 0 6 0 7 0 [7] reserved [0] reserved [6] reserved [1] reserved [5] reserved [2] reserved [4] ref_buf_pos_en (r/w ) [3] ref_buf_neg_en (r/w ) table 69. bit descriptions for buffer_config_1 bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ref_buf_pos_en reference buffer positive enable 0x1 r/w 3 ref_buf_neg_en reference buffer negative enable 0x1 r/w [2:0] reserved reserved 0x0 r/w buffer configuration 2 register address: 0x01a, reset: 0xc0, name: buffer_config_2 reference buffer positive precharge enable dregcap overdrive enable. reference buffer negative precharge enable areg2cap overdrive enable areg1cap overdrive enable 0 0 1 0 2 0 3 0 4 0 5 0 6 1 7 1 [7] refbufp_preq (r/w) [0] pdb_dldo_ovrdrv (r/w) [6] refbufn_preq (r/w ) [1] pdb_aldo2_ovrdrv (r/w ) [5:3] reserved [2] pdb_aldo1_ovrdrv (r/w ) table 70. bit descriptions for buffer_config_2 bits bit name settings description reset access 7 refbufp_preq reference buffer positive precharge enable 0x1 r/w 6 refbufn_preq reference buffer negative precharge enable 0x1 r/w [5:3] reserved reserved 0x0 r/w 2 pdb_aldo1_ovrdrv areg1cap overdrive enable 0x0 r/w 1 pdb_aldo2_ovrdrv areg2cap overdrive enable 0x0 r/w 0 pdb_dldo_ovrdrv dregcap overdrive enable 0x0 r/w
data sheet ad7771 rev. 0 | page 77 of 98 channel 0 offset upper byte register address: 0x01c, reset: 0x00, name: ch0_offset_upper_byte combined offset register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_offset_all[23:16] (r/w) table 71. bit descriptions for ch0_offset_upper_byte bits bit name settings description reset access [7:0] ch0_offset_all[23:16] combined offset register channel 0 0x0 r/w channel 0 offset middle byte register address: 0x01d, reset: 0x00, name: ch0_offset_mid_byte combined offset register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_offset_all[15:8] (r/w) table 72. bit descriptions for ch0_offset_mid_byte bits bit name settings description reset access [7:0] ch0_offset_all[15:8] combined offset register channel 0 0x0 r/w channel 0 offset lower byte register address: 0x01e, reset: 0x00, name: ch0_offset_lower_byte combined offset register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_offset_all[7:0] (r/w) table 73. bit descriptions for ch0_offset_lower_byte bits bit name settings description reset access [7:0] ch0_offset_all[7:0] combined offset register channel 0 0x0 r/w channel 0 gain upper byte register address: 0x01f, reset: 0x00, name: ch0_gain_upper_byte combined gain register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_gain_all[23:16] (r/w ) table 74. bit descriptions for ch0_gain_upper_byte bits bit name settings description reset access [7:0] ch0_gain_all[23:16] combined gain register channel 0 0x0 r/w channel 0 gain middle byte register address: 0x020, reset: 0x00, name: ch0_gain_mid_byte combined gain register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_gain_all[15:8] (r/w) table 75. bit descriptions for ch0_gain_mid_byte bits bit name settings description reset access [7:0] ch0_gain_all[15:8] combined gain register channel 0 0x0 r/w
ad7771 data sheet rev. 0 | page 78 of 98 channel 0 gain lower byte register address: 0x021, reset: 0x00, name: ch0_gain_lower_byte combined gain register channel 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch0_gain_all[7:0] (r/w ) table 76. bit descriptions for ch0_gain_lower_byte bits bit name settings description reset access [7:0] ch0_gain_all[7:0] combined gain register channel 0 0x0 r/w channel 1 offset upper byte register address: 0x022, reset: 0x00, name: ch1_offset_upper_byte combined offset register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_offset_all[23:16] (r/w) table 77. bit descriptions for ch1_offset_upper_byte bits bit name settings description reset access [7:0] ch1_offset_all[23:16] combined offset register channel 1 0x0 r/w channel 1 offset middle byte register address: 0x023, reset: 0x00, name: ch1_offset_mid_byte combined offset register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_offset_all[15:8] (r/w) table 78. bit descriptions for ch1_offset_mid_byte bits bit name settings description reset access [7:0] ch1_offset_all[15:8] combined offset register channel 1 0x0 r/w channel 1 offset lower byte register address: 0x024, reset: 0x00, name: ch1_offset_lower_byte combined offset register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_offset_all[7:0] (r/w) table 79. bit descriptions for ch1_offset_lower_byte bits bit name settings description reset access [7:0] ch1_offset_all[7:0] combined offset register channel 1 0x0 r/w channel 1 gain upper byte register address: 0x025, reset: 0x00, name: ch1_gain_upper_byte combined gain register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_gain_all[23:16] (r/w ) table 80. bit descriptions for ch1_gain_upper_byte bits bit name settings description reset access [7:0] ch1_gain_all[23:16] combined gain register channel 1 0x0 r/w
data sheet ad7771 rev. 0 | page 79 of 98 channel 1 gain middle byte register address: 0x026, reset: 0x00, name: ch1_gain_mid_byte combined gain register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_gain_all[15:8] (r/w) table 81. bit descriptions for ch1_gain_mid_byte bits bit name settings description reset access [7:0] ch1_gain_all[15:8] combined gain register channel 1 0x0 r/w channel 1 gain lower byte register address: 0x027, reset: 0x00, name: ch1_gain_lower_byte combined gain register channel 1 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch1_gain_all[7:0] (r/w ) table 82. bit descriptions for ch1_gain_lower_byte bits bit name settings description reset access [7:0] ch1_gain_all[7:0] combined gain register channel 1 0x0 r/w channel 2 offset upper byte register address: 0x028, reset: 0x00, name: ch2_offset_upper_byte combined offset register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_offset_all[23:16] (r/w) table 83. bit descriptions for ch2_offset_upper_byte bits bit name settings description reset access [7:0] ch2_offset_all[23:16] combined offset register channel 2 0x0 r/w channel 2 offset middle byte register address: 0x029, reset: 0x00, name: ch2_offset_mid_byte combined offset register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_offset_all[15:8] (r/w) table 84. bit descriptions for ch2_offset_mid_byte bits bit name settings description reset access [7:0] ch2_offset_all[15:8] combined offset register channel 2 0x0 r/w channel 2 offset lower byte register address: 0x02a, reset: 0x00, name: ch2_offset_lower_byte combined offset register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_offset_all[7:0] (r/w) table 85. bit descriptions for ch2_offset_lower_byte bits bit name settings description reset access [7:0] ch2_offset_all[7:0] combined offset register channel 2 0x0 r/w
ad7771 data sheet rev. 0 | page 80 of 98 channel 2 gain upper byte register address: 0x02b, reset: 0x00, name: ch2_gain_upper_byte combined gain register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_gain_all[23:16] (r/w ) table 86. bit descriptions for ch2_gain_upper_byte bits bit name settings description reset access [7:0] ch2_gain_all[23:16] combined gain register channel 2 0x0 r/w channel 2 gain middle byte register address: 0x02c, reset: 0x00, name: ch2_gain_mid_byte combined gain register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_gain_all[15:8] (r/w) table 87. bit descriptions for ch2_gain_mid_byte bits bit name settings description reset access [7:0] ch2_gain_all[15:8] combined gain register channel 2 0x0 r/w channel 2 gain lower byte register address: 0x02d, reset: 0x00, name: ch2_gain_lower_byte combined gain register channel 2 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch2_gain_all[7:0] (r/w ) table 88. bit descriptions for ch2_gain_lower_byte bits bit name settings description reset access [7:0] ch2_gain_all[7:0] combined gain register channel 2 0x0 r/w channel 3 offset upper byte register address: 0x02e, reset: 0x00, name: ch3_offset_upper_byte combined offset register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_offset_all[23:16] (r/w) table 89. bit descriptions for ch3_offset_upper_byte bits bit name settings description reset access [7:0] ch3_offset_all[23:16] combined offset register channel 3 0x0 r/w channel 3 offset middle byte register address: 0x02f, reset: 0x00, name: ch3_offset_mid_byte combined offset register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_offset_all[15:8] (r/w) table 90. bit descriptions for ch3_offset_mid_byte bits bit name settings description reset access [7:0] ch3_offset_all[15:8] combined offset register channel 3 0x0 r/w
data sheet ad7771 rev. 0 | page 81 of 98 channel 3 offset lower byte register address: 0x030, reset: 0x00, name: ch3_offset_lower_byte combined offset register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_offset_all[7:0] (r/w) table 91. bit descriptions for ch3_offset_lower_byte bits bit name settings description reset access [7:0] ch3_offset_all[7:0] combined offset register channel 3 0x0 r/w channel 3 gain upper byte register address: 0x031, reset: 0x00, name: ch3_gain_upper_byte combined gain register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_gain_all[23:16] (r/w ) table 92. bit descriptions for ch3_gain_upper_byte bits bit name settings description reset access [7:0] ch3_gain_all[23:16] combined gain register channel 3 0x0 r/w channel 3 gain middle byte register address: 0x032, reset: 0x00, name: ch3_gain_mid_byte combined gain register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_gain_all[15:8] (r/w) table 93. bit descriptions for ch3_gain_mid_byte bits bit name settings description reset access [7:0] ch3_gain_all[15:8] combined gain register channel 3 0x0 r/w channel 3 gain lower byte register address: 0x033, reset: 0x00, name: ch3_gain_lower_byte combined gain register channel 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch3_gain_all[7:0] (r/w ) table 94. bit descriptions for ch3_gain_lower_byte bits bit name settings description reset access [7:0] ch3_gain_all[7:0] combined gain register channel 3 0x0 r/w channel 4 offset upper byte register address: 0x034, reset: 0x00, name: ch4_offset_upper_byte combined offset register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_offset_all[23:16] (r/w) table 95. bit descriptions for ch4_offset_upper_byte bits bit name settings description reset access [7:0] ch4_offset_all[23:16] combined offset register channel 4 0x0 r/w
ad7771 data sheet rev. 0 | page 82 of 98 channel 4 offset middle byte register address: 0x035, reset: 0x00, name: ch4_offset_mid_byte combined offset register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_offset_all[15:8] (r/w) table 96. bit descriptions for ch4_offset_mid_byte bits bit name settings description reset access [7:0] ch4_offset_all[15:8] combined offset register channel 4 0x0 r/w channel 4 offset lower byte register address: 0x036, reset: 0x00, name: ch4_offset_lower_byte combined offset register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_offset_all[7:0] (r/w) table 97. bit descriptions for ch4_offset_lower_byte bits bit name settings description reset access [7:0] ch4_offset_all[7:0] combined offset register channel 4 0x0 r/w channel 4 gain upper byte register address: 0x037, reset: 0x00, name: ch4_gain_upper_byte combined gain register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_gain_all[23:16] (r/w ) table 98. bit descriptions for ch4_gain_upper_byte bits bit name settings description reset access [7:0] ch4_gain_all[23:16] combined gain register channel 4 0x0 r/w channel 4 gain middle byte register address: 0x038, reset: 0x00, name: ch4_gain_mid_byte combined gain register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_gain_all[15:8] (r/w) table 99. bit descriptions for ch4_gain_mid_byte bits bit name settings description reset access [7:0] ch4_gain_all[15:8] combined gain register channel 4 0x0 r/w channel 4 gain lower byte register address: 0x039, reset: 0x00, name: ch4_gain_lower_byte combined gain register channel 4 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch4_gain_all[7:0] (r/w ) table 100. bit descriptions for ch4_gain_lower_byte bits bit name settings description reset access [7:0] ch4_gain_all[7:0] combined gain register channel 4 0x0 r/w
data sheet ad7771 rev. 0 | page 83 of 98 channel 5 offset upper byte register address: 0x03a, reset: 0x00, name: ch5_offset_upper_byte combined offset register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_offset_all[23:16] (r/w) table 101. bit descriptions for ch5_offset_upper_byte bits bit name settings description reset access [7:0] ch5_offset_all[23:16] combined offset register channel 5 0x0 r/w channel 5 offset middle byte register address: 0x03b, reset: 0x00, name: ch5_offset_mid_byte combined offset register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_offset_all[15:8] (r/w) table 102. bit descriptions for ch5_offset_mid_byte bits bit name settings description reset access [7:0] ch5_offset_all[15:8] combined offset register channel 5 0x0 r/w channel 5 offset lower byte register address: 0x03c, reset: 0x00, name: ch5_offset_lower_byte combined offset register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_offset_all[7:0] (r/w) table 103. bit descriptions for ch5_offset_lower_byte bits bit name settings description reset access [7:0] ch5_offset_all[7:0] combined offset register channel 5 0x0 r/w channel 5 gain upper byte register address: 0x03d, reset: 0x00, name: ch5_gain_upper_byte combined gain register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_gain_all[23:16] (r/w ) table 104. bit descriptions for ch5_gain_upper_byte bits bit name settings description reset access [7:0] ch5_gain_all[23:16] combined gain register channel 5 0x0 r/w channel 5 gain middle byte register address: 0x03e, reset: 0x00, name: ch5_gain_mid_byte combined gain register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_gain_all[15:8] (r/w) table 105. bit descriptions for ch5_gain_mid_byte bits bit name settings description reset access [7:0] ch5_gain_all[15:8] combined gain register channel 5 0x0 r/w
ad7771 data sheet rev. 0 | page 84 of 98 channel 5 gain lower byte register address: 0x03f, reset: 0x00, name: ch5_gain_lower_byte combined gain register channel 5 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch5_gain_all[7:0] (r/w ) table 106. bit descriptions for ch5_gain_lower_byte bits bit name settings description reset access [7:0] ch5_gain_all[7:0] combined gain register channel 5 0x0 r/w channel 6 offset upper byte register address: 0x040, reset: 0x00, name: ch6_offset_upper_byte combined offset register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_offset_all[23:16] (r/w) table 107. bit descriptions for ch6_offset_upper_byte bits bit name settings description reset access [7:0] ch6_offset_all[23:16] combined offset register channel 6 0x0 r/w channel 6 offset middle byte register address: 0x041, reset: 0x00, name: ch6_offset_mid_byte combined offset register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_offset_all[15:8] (r/w) table 108. bit descriptions for ch6_offset_mid_byte bits bit name settings description reset access [7:0] ch6_offset_all[15:8] combined offset register channel 6 0x0 r/w channel 6 offset lower byte register address: 0x042, reset: 0x00, name: ch6_offset_lower_byte combined offset register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_offset_all[7:0] (r/w) table 109. bit descriptions for ch6_offset_lower_byte bits bit name settings description reset access [7:0] ch6_offset_all[7:0] combined offset register channel 6 0x0 r/w channel 6 gain upper byte register address: 0x043, reset: 0x00, name: ch6_gain_upper_byte combined gain register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_gain_all[23:16] (r/w ) table 110. bit descriptions for ch6_gain_upper_byte bits bit name settings description reset access [7:0] ch6_gain_all[23:16] combined gain register channel 6 0x0 r/w
data sheet ad7771 rev. 0 | page 85 of 98 channel 6 gain middle byte register address: 0x044, reset: 0x00, name: ch6_gain_mid_byte combined gain register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_gain_all[15:8] (r/w) table 111. bit descriptions for ch6_gain_mid_byte bits bit name settings description reset access [7:0] ch6_gain_all[15:8] combined gain register channel 6 0x0 r/w channel 6 gain lower byte register address: 0x045, reset: 0x00, name: ch6_gain_lower_byte combined gain register channel 6 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch6_gain_all[7:0] (r/w ) table 112. bit descriptions for ch6_gain_lower_byte bits bit name settings description reset access [7:0] ch6_gain_all[7:0] combined gain register channel 6 0x0 r/w channel 7 offset upper byte register address: 0x046, reset: 0x00, name: ch7_offset_upper_byte combined offset register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_offset_all[23:16] (r/w) table 113. bit descriptions for ch7_offset_upper_byte bits bit name settings description reset access [7:0] ch7_offset_all[23:16] combined offset register channel 7 0x0 r/w channel 7 offset middle byte register address: 0x047, reset: 0x00, name: ch7_offset_mid_byte combined offset register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_offset_all[15:8] (r/w) table 114. bit descriptions for ch7_offset_mid_byte bits bit name settings description reset access [7:0] ch7_offset_all[15:8] combined offset register channel 7 0x0 r/w channel 7 offset lower byte register address: 0x048, reset: 0x00, name: ch7_offset_lower_byte combined offset register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_offset_all[7:0] (r/w) table 115. bit descriptions for ch7_offset_lower_byte bits bit name settings description reset access [7:0] ch7_offset_all[7:0] combined offset register channel 7 0x0 r/w
ad7771 data sheet rev. 0 | page 86 of 98 channel 7 gain upper byte register address: 0x049, reset: 0x00, name: ch7_gain_upper_byte combined gain register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_gain_all[23:16] (r/w ) table 116. bit descriptions for ch7_gain_upper_byte bits bit name settings description reset access [7:0] ch7_gain_all[23:16] combined gain register channel 7 0x0 r/w channel 7 gain middle byte register address: 0x04a, reset: 0x00, name: ch7_gain_mid_byte combined gain register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_gain_all[15:8] (r/w) table 117. bit descriptions for ch7_gain_mid_byte bits bit name settings description reset access [7:0] ch7_gain_all[15:8] combined gain register channel 7 0x0 r/w channel 7 gain lower byte register address: 0x04b, reset: 0x00, name: ch7_gain_lower_byte combined gain register channel 7 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] ch7_gain_all[7:0] (r/w ) table 118. bit descriptions for ch7_gain_lower_byte bits bit name settings description reset access [7:0] ch7_gain_all[7:0] combined gain register channel 7 0x0 r/w channel 0 status register address: 0x04c, reset: 0x00, name: ch0_err_reg channel 0 - reference detect error a in0- undervoltage error ain0+ overvoltage error a in0- overvoltage error ain0+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch0_err_ref_det (r) [4] ch0_err_ainm_uv (r) [1] ch0_err_ainp_ov (r) [3] ch0_err_ainm_ov (r) [2] ch0_err_ainp_uv (r) table 119. bit descriptions for ch0_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch0_err_ainm_uv channel 0ain0? undervoltage error 0x0 r 3 ch0_err_ainm_ov channel 0ain0? overvoltage error 0x0 r 2 ch0_err_ainp_uv channel 0ain0+ undervoltage error 0x0 r 1 ch0_err_ainp_ov channel 0ain0+ overvoltage error 0x0 r 0 ch0_err_ref_det channel 0reference detect error 0x0 r
data sheet ad7771 rev. 0 | page 87 of 98 channel 1 status register address: 0x04d, reset: 0x00, name: ch1_err_reg channel 1 - reference detect error a in1- undervoltage error ain1+ overvoltage error a in1- overvoltage error ain1+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch1_err_ref_det (r) [4] ch1_err_ainm_uv (r) [1] ch1_err_ainp_ov (r) [3] ch1_err_ainm_ov (r) [2] ch1_err_ainp_uv (r) table 120. bit descriptions for ch1_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch1_err_ainm_uv channel 1ain1? undervoltage error 0x0 r 3 ch1_err_ainm_ov channel 1ain1? overvoltage error 0x0 r 2 ch1_err_ainp_uv channel 1ain1+ undervoltage error 0x0 r 1 ch1_err_ainp_ov channel 1ain1+ overvoltage error 0x0 r 0 ch1_err_ref_det channel 1reference detect error 0x0 r channel 2 status register address: 0x04e, reset: 0x00, name: ch2_err_reg channel 2 - reference detect error a in2- undervoltage error ain2+ overvoltage error a in2- overvoltage error ain2+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch2_err_ref_det (r) [4] ch2_err_ainm_uv (r) [1] ch2_err_ainp_ov (r) [3] ch2_err_ainm_ov (r) [2] ch2_err_ainp_uv (r) table 121. bit descriptions for ch2_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch2_err_ainm_uv channel 2ain2? undervoltage error 0x0 r 3 ch2_err_ainm_ov channel 2ain2? overvoltage error 0x0 r 2 ch2_err_ainp_uv channel 2ain2+ undervoltage error 0x0 r 1 ch2_err_ainp_ov channel 2ain2+ overvoltage error 0x0 r 0 ch2_err_ref_det channel 2reference detect error 0x0 r
ad7771 data sheet rev. 0 | page 88 of 98 channel 3 status register address: 0x04f, reset: 0x00, name: ch3_err_reg channel 3 - reference detect error a in3- undervoltage error ain3+ overvoltage error a in3- overvoltage error ain3+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch3_err_ref_det (r) [4] ch3_err_ainm_uv (r) [1] ch3_err_ainp_ov (r) [3] ch3_err_ainm_ov (r) [2] ch3_err_ainp_uv (r) table 122. bit descriptions for ch3_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch3_err_ainm_uv channel 3ain3? undervoltage error 0x0 r 3 ch3_err_ainm_ov channel 3ain3? overvoltage error 0x0 r 2 ch3_err_ainp_uv channel 3ain3+ undervoltage error 0x0 r 1 ch3_err_ainp_ov channel 3ain3+ overvoltage error 0x0 r 0 ch3_err_ref_det channel 3reference detect error 0x0 r channel 4 status register address: 0x050, reset: 0x00, name: ch4_err_reg channel 4 - reference detect error a in4- undervoltage error ain4+ overvoltage error a in4- overvoltage error ain4+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch4_err_ref_det (r) [4] ch4_err_ainm_uv (r) [1] ch4_err_ainp_ov (r) [3] ch4_err_ainm_ov (r) [2] ch4_err_ainp_uv (r) table 123. bit descriptions for ch4_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch4_err_ainm_uv channel 4ain4? undervoltage error 0x0 r 3 ch4_err_ainm_ov channel 4ain4? overvoltage error 0x0 r 2 ch4_err_ainp_uv channel 4ain4+ undervoltage error 0x0 r 1 ch4_err_ainp_ov channel 4ain4+ overvoltage error 0x0 r 0 ch4_err_ref_det channel 4reference detect error 0x0 r
data sheet ad7771 rev. 0 | page 89 of 98 channel 5 status register address: 0x051, reset: 0x00, name: ch5_err_reg channel 5 - reference detect error a in5- undervoltage error ain5+ overvoltage error a in5- overvoltage error ain5+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch5_err_ref_det (r) [4] ch5_err_ainm_uv (r) [1] ch5_err_ainp_ov (r) [3] ch5_err_ainm_ov (r) [2] ch5_err_ainp_uv (r) table 124. bit descriptions for ch5_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch5_err_ainm_uv channel 5ain5? undervoltage error 0x0 r 3 ch5_err_ainm_ov channel 5ain5? overvoltage error 0x0 r 2 ch5_err_ainp_uv channel 5ain5+ undervoltage error 0x0 r 1 ch5_err_ainp_ov channel 5ain5+ overvoltage error 0x0 r 0 ch5_err_ref_det channel 5reference detect error 0x0 r channel 6 status register address: 0x052, reset: 0x00, name: ch6_err_reg channel 6 - reference detect error a in6- undervoltage error ain6+ overvoltage error a in6- overvoltage error ain6+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch6_err_ref_det (r) [4] ch6_err_ainm_uv (r) [1] ch6_err_ainp_ov (r) [3] ch6_err_ainm_ov (r) [2] ch6_err_ainp_uv (r) table 125. bit descriptions for ch6_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r/w 4 ch6_err_ainm_uv channel 6ain6? undervoltage error 0x0 r 3 ch6_err_ainm_ov channel 6ain6? overvoltage error 0x0 r 2 ch6_err_ainp_uv channel 6ain6+ undervoltage error 0x0 r 1 ch6_err_ainp_ov channel 6ain6+ overvoltage error 0x0 r 0 ch6_err_ref_det channel 6reference detect error 0x0 r
ad7771 data sheet rev. 0 | page 90 of 98 channel 7 status register address: 0x053, reset: 0x00, name: ch7_err_reg channel 7 - reference detect error a in7- undervoltage error ain7+ overvoltage error a in7- overvoltage error ain7+ undervoltage error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [0] ch7_err_ref_det (r) [4] ch7_err_ainm_uv (r) [1] ch7_err_ainp_ov (r) [3] ch7_err_ainm_ov (r) [2] ch7_err_ainp_uv (r) table 126. bit descriptions for ch7_err_reg bits bit name settings description reset access [7:5] reserved reserved 0x0 r 4 ch7_err_ainm_uv channel 7ain7? undervoltage error 0x0 r 3 ch7_err_ainm_ov channel 7ain7? overvoltage error 0x0 r 2 ch7_err_ainp_uv channel 7ain7+ undervoltage error 0x0 r 1 ch7_err_ainp_ov channel 7ain7+ overvoltage error 0x0 r 0 ch7_err_ref_det channel 7reference detect error 0x0 r channel 0/channel 1 dsp errors register address: 0x054, reset: 0x00, name: ch0_1_sat_err channel 0 - adc conversion has exceeded limits and has been clamped channel 1 - modulator output saturation error channel 0 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 1 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 0 - modulator output saturation error channel 1 - adc conversion has exceeded limits and has been clamped 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] ch0_err_output_sat (r) [5] ch1_err_mod_sat (r) [1] ch0_err_filter_sat (r) [4] ch1_err_filter_sat (r) [2] ch0_err_mod_sat (r) [3] ch1_err_output_sat (r) table 127. bit descriptions for ch0_1_sat_err bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 ch1_err_mod_sat channel 1modulator output saturation error 0x0 r 4 ch1_err_filter_sat channel 1filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 3 ch1_err_output_sat channel 1adc conversi on has exceeded limits and is clamped 0x0 r 2 ch0_err_mod_sat channel 0modulator output saturation error 0x0 r 1 ch0_err_filter_sat channel 0filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 0 ch0_err_output_sat channel 0adc conversi on has exceeded limits and is clamped 0x0 r
data sheet ad7771 rev. 0 | page 91 of 98 channel 2/channel 3 dsp errors register address: 0x055, reset: 0x00, name: ch2_3_sat_err channel 2 - adc conversion has exceeded limits and has been clamped channel 3 - modulator output saturation error channel 2 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 3 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 2 - modulator output saturation error channel 3 - adc conversion has exceeded limits and has been clamped 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] ch2_err_output_sat (r) [5] ch3_err_mod_sat (r) [1] ch2_err_filter_sat (r) [4] ch3_err_filter_sat (r) [2] ch2_err_mod_sat (r) [3] ch3_err_output_sat (r) table 128. bit descriptions for ch2_3_sat_err bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 ch3_err_mod_sat channel 3modulator output saturation error 0x0 r 4 ch3_err_filter_sat channel 3filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 3 ch3_err_output_sat channel 3adc conversi on has exceeded limits and is clamped 0x0 r 2 ch2_err_mod_sat channel 2modulator output saturation error 0x0 r 1 ch2_err_filter_sat channel 2filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 0 ch2_err_output_sat channel 2adc conversion has exceeded limits and has been clamped 0x0 r channel 4/channel 5 dsp errors register address: 0x056, reset: 0x00, name: ch4_5_sat_err channel 4 - adc conversion has exceeded limits and has been clamped channel 5 - modulator output saturation error channel 4 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 5 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 4 - modulator output saturation error channel 5 - adc conversion has exceeded limits and has been clamped 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] ch4_err_output_sat (r) [5] ch5_err_mod_sat (r) [1] ch4_err_filter_sat (r) [4] ch5_err_filter_sat (r) [2] ch4_err_mod_sat (r) [3] ch5_err_output_sat (r) table 129. bit descriptions for ch4_5_sat_err bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 ch5_err_mod_sat channel 5modulator output saturation error 0x0 r 4 ch5_err_filter_sat channel 5filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 3 ch5_err_output_sat channel 5adc conversi on has exceeded limits and is clamped 0x0 r 2 ch4_err_mod_sat channel 4modulator output saturation error 0x0 r 1 ch4_err_filter_sat channel 4filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 0 ch4_err_output_sat channel 4adc conversi on has exceeded limits and is clamped 0x0 r
ad7771 data sheet rev. 0 | page 92 of 98 channel 6/channel 7 dsp errors register address: 0x057, reset: 0x00, name: ch6_7_sat_err channel 6 - adc conversion has exceeded limits and has been clamped channel 7 - modulator output saturation error channel 6 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 7 - filter result has exceeded a reasonable level, before offset and gain calibration has been applied. channel 6 - modulator output saturation error channel 7 - adc conversion has exceeded limits and has been clamped 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] ch6_err_output_sat (r) [5] ch7_err_mod_sat (r) [1] ch6_err_filter_sat (r) [4] ch7_err_filter_sat (r) [2] ch6_err_mod_sat (r) [3] ch7_err_output_sat (r) table 130. bit descriptions for ch6_7_sat_err bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 ch7_err_mod_sat channel 7modulator output saturation error 0x0 r 4 ch7_err_filter_sat channel 7filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 3 ch7_err_output_sat channel 7adc conversi on has exceeded limits and is clamped 0x0 r 2 ch6_err_mod_sat channel 6modulator output saturation error 0x0 r 1 ch6_err_filter_sat channel 6filter result has exceeded a reasonable level, before offset and gain calibration are applied 0x0 r 0 ch6_err_output_sat channel 6adc conversi on has exceeded limits and is clamped 0x0 r channel 0 to channel 7 error register enable register address: 0x058, reset: 0xfe, name: chx_err_reg_en a dc conversion error test enable reference detect test enable filter saturation error test enable ainx+ overvoltage test enable enable error flag for modulator saturation ainx+ undervoltage test enable a inx- undervoltage test enable ainx- overvoltage test enable 0 0 1 1 2 1 3 1 4 1 5 1 6 1 7 1 [7] output_sat_test_en (r/w) [0] ref_det_test_en (r/w) [6] filter_sat_test_en (r/w) [1] ainp_ov_test_en (r/w) [5] mod_sat_test_en (r/w) [2] ainp_uv_test_en (r/w) [4] ainm_uv_test_en (r/w) [3] ainm_ov_test_en (r/w) table 131. bit descriptions for chx_err_reg_en bits bit name settings description reset access 7 output_sat_test_en adc conver sion error test enable 0x1 r/w 6 filter_sat_test_en filter saturation test enable 0x1 r/w 5 mod_sat_test_en enable error flag for modulator saturation 0x1 r/w 4 ainm_uv_test_en ainx? undervoltage test enable 0x1 r/w 3 ainm_ov_test_en ainx? overvoltage test enable 0x1 r/w 2 ainp_uv_test_en ainx+ undervoltage test enable 0x1 r/w 1 ainp_ov_test_en ainx+ overvoltage test enable 0x1 r/w 0 ref_det_test_en reference detect test enable 0x0 r/w
data sheet ad7771 rev. 0 | page 93 of 98 general errors register 1 address: 0x059, reset: 0x00, name: gen_err_reg_1 spi crc error a crc of the m em ory m ap contents is run periodically to check for errors spi invalid write address a crc of the fus e contents is run periodically to check for errors in the fus es spi invalid read address spi clock counter error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] spi_crc_err (r) [5] memmap_crc_err (r) [1] spi_invalid_write_err (r ) [4] rom_crc_err (r) [2] spi_invalid_read_err (r) [3] spi_clk_count_err (r) table 132. bit descriptions for gen_err_reg_1 bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 memmap_crc_err a crc of the memory map contents is run periodically to check for errors 0x0 r 4 rom_crc_err a crc of the fuse contents is run pe riodically to check for er rors in the fuses 0x0 r 3 spi_clk_count_err spi clock counter error 0x0 r 2 spi_invalid_read_err spi invalid read address 0x0 r 1 spi_invalid_write_err spi invalid write address 0x0 r 0 spi_crc_err spi crc error 0x0 r general errors register 1 enable address: 0x05a, reset: 0x3e, name: gen_err_reg_1_en table 133. bit descriptions for gen_err_reg_1_en bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 memmap_crc_test_en memory map crc test error enable 0x1 r/w 4 rom_crc_test_en fuse crc test enable 0x1 r/w 3 spi_clk_count_test_en spi clock counter test enable 0x1 r/w 2 spi_invalid_read_test_en spi invalid read address test enable 0x1 r/w 1 spi_invalid_write_test_en spi invalid write address test enable 0x1 r/w 0 spi_crc_test_en spi crc error test enable 0x0 r/w
ad7771 data sheet rev. 0 | page 94 of 98 general errors register 2 address: 0x05b, reset: 0x00, name: gen_err_reg_2 dregcap power supply error reset detected areg2cap power supply error clock not switched over areg1cap power supply error 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] dldo_psm_err (r) [5] reset_detected (r) [1] aldo2_psm_err (r) [4] ext_mclk_switch_err (r) [2] aldo1_psm_err (r) [3] reserved table 134. bit descriptions for gen_err_reg_2 bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 reset_detected reset detected 0x0 r 4 ext_mclk_switch_err clock not switched over 0x0 r 3 reserved reserved 0x0 r 2 aldo1_psm_err areg1cap power supply error 0x0 r 1 aldo2_psm_err areg2cap power supply error 0x0 r 0 dldo_psm_err dregcap power supply error 0x0 r general errors register 2 enable address: 0x05c, reset: 0x3c, name: gen_err_reg_2_en ldo psm trip tes t enable 11: 11 - run trip detect tes t on dregcap. 10: 10 - run trip detect tes t on areg2cap . 1: 01 - run trip detect tes t on areg1cap . 0: 00 - no trip detect tes t enabled. reset detect enable ldo psm test en 11: on all ldos. 11 - run power supply monitor test 10: on dregcap. 10 - run power supply monitor test 1: on aregxcap. 01 - run power supply monitor test 0: enabled. 00 - no power supply monitor test 0 0 1 0 2 1 3 1 4 0 5 1 6 0 7 0 [7:6] reserved [1:0] ldo_psm_trip_test_en (r/w) [5] reset_detect_en (r/w ) [3:2] ldo_psm_test_en (r/w) [4] reserved table 135. bit descriptions for gen_err_reg_2_en bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 reset_detect_en reset detect enable 0x1 r/w 4 reserved reserved 0x1 r/w [3:2] ldo_psm_test_en ldo psm test enable 0x3 r/w 0 00no power supply monitor test enabled 1 01run power supply monitor test on aregxcap 10 10run power supply monitor test on dregcap 11 11run power supply monitor test on all ldos [1:0] ldo_psm_trip_test_en ldo psm trip test enable 0x0 r/w 0 00no trip detect test enabled 1 01run trip detect test on areg1cap 10 10run trip detect test on areg2cap 11 11run trip detect test on dregcap
data sheet ad7771 rev. 0 | page 95 of 98 error status register 1 address: 0x05d, reset: 0x00, name: status_reg_1 an error specific to ch0_err_reg is active set high if any error bit is high an error specific to ch1_err_reg is active a n error specific to ch4_err_reg is active an error specific to ch2_err_reg is active a n error specific to ch3_err_reg is active 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] err_loc_ch0 (r) [5] chip_error (r) [1] err_loc_ch1 (r) [4] err_loc_ch4 (r) [2] err_loc_ch2 (r) [3] err_loc_ch3 (r) table 136. bit descriptions for status_reg_1 bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 chip_error set this bit high if any error bit is high 0x0 r 4 err_loc_ch4 an error specific to ch4_err_reg is active 0x0 r 3 err_loc_ch3 an error specific to ch3_err_reg is active 0x0 r 2 err_loc_ch2 an error specific to ch2_err_reg is active 0x0 r 1 err_loc_ch1 an error specific to ch1_err_reg is active 0x0 r 0 err_loc_ch0 an error specific to ch0_err_reg is active 0x0 r error status register 2 address: 0x05e, reset: 0x00, name: status_reg_2 an error specific to ch5_err_reg is active set high if any error bit is high an error specific to ch6_err_reg is active a n error specific to gen_err_reg_2 is active an error specific to ch7_err_reg is active a n error specific to gen_err_reg_1 is active 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] err_loc_ch5 (r) [5] chip_error (r) [1] err_loc_ch6 (r) [4] err_loc_gen2 (r) [2] err_loc_ch7 (r) [3] err_loc_gen1 (r) table 137. bit descriptions for status_reg_2 bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 chip_error set high if any error bit is high 0x0 r 4 err_loc_gen2 an error specific to gen_err_reg_2 is active 0x0 r 3 err_loc_gen1 an error specific to gen_err_reg_1 is active 0x0 r 2 err_loc_ch7 an error specific to ch7_err_reg is active 0x0 r 1 err_loc_ch6 an error specific to ch6_err_reg is active 0x0 r 0 err_loc_ch5 an error specific to ch5_err_reg is active 0x0 r
ad7771 data sheet rev. 0 | page 96 of 98 error status register 3 address: 0x05f, reset: 0x00, name: status_reg_3 an error specific to ch0_1_sat_er r reg is active set high if any error bit is high an error specific to ch2_3_sat_er r reg is active fuse initialization is complete. device is ready to receive commands an error specific to ch4_5_sat_er r reg is active a n error specific to ch6_7_sat_err reg is active 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [0] err_loc_sat_ch0_1 (r) [5] chip_error (r) [1] err_loc_sat_ch2_3 (r) [4] init_complete (r) [2] err_loc_sat_ch4_5 (r) [3] err_loc_sat_ch6_7 (r) table 138. bit descriptions for status_reg_3 bits bit name settings description reset access [7:6] reserved reserved 0x0 r 5 chip_error set high if any error bit is high. 0x0 r 4 init_complete fuse initialization is comple te. device is ready to receive commands. 0x0 r 3 err_loc_sat_ch6_7 an error specific to ch6_7_sat_err register is active. 0x0 r 2 err_loc_sat_ch4_5 an error specific to ch4_5_sat_err register is active. 0x0 r 1 err_loc_sat_ch2_3 an error specific to ch2_3_sat_err register is active. 0x0 r 0 err_loc_sat_ch0_1 an error specific to ch0_1_sat_err register is active. 0x0 r decimation rate (n) msb register address: 0x060, reset: 0x00, name: src_n_msb src n combined 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:4] reserved [3:0] src_n_all[11:8] (r/w ) table 139. bit descriptions for src_n_msb bits bit name settings description reset access [7:4] reserved reserved 0x0 r [3:0] src_n_all[11:8] src n combined 0x0 r/w decimation rate (n) lsb register address: 0x061, reset: 0x80, name: src_n_lsb src n combined 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 1 [7:0] src_n_all[7:0] (r/w ) table 140. bit descriptions for src_n_lsb bits bit name settings description reset access [7:0] src_n_all[7:0] src n combined 0x0 r/w decimation rate (if) msb register address: 0x062, reset: 0x00, name: src_if_msb src if all 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] src_if_all[15:8] (r/w) table 141. bit descriptions for src_if_msb bits bit name settings description reset access [7:0] src_if_all[15:8] src if all 0x0 r/w
data sheet ad7771 rev. 0 | page 97 of 98 decimation rate (if) lsb register address: 0x063, reset: 0x00, name: src_if_lsb src if all 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] src_if_all[7:0] (r/w) table 142. bit descriptions for src_if_lsb bits bit name settings description reset access [7:0] src_if_all[7:0] src if all 0x0 r/w src load source and load update register address: 0x064, reset: 0x00, name: src_update select which option to load an src update as s ert bit to load src regis ters into src 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7] src_load_source (r/w ) [0] src_load_update (r/w ) [6:1] reserved table 143. bit descriptions for src_update bits bit name settings description reset access 7 src_load_source selects which opti on to load an src update 0x0 r/w [6:1] reserved reserved 0x0 r 0 src_load_update asserts bit to load src registers into src 0x0 r/w
ad7771 data sheet rev. 0 | page 98 of 98 outline dimensions 0.50 bsc bottom view top view pin 1 indicator exposed pad p i n 1 i n d i c a t o r 7.70 7.60 sq 7.50 0.45 0.40 0.35 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.18 02-12-2014-a 9.10 9.00 sq 8.90 0.20 min 7.50 ref compliant to jedec standards mo-220-wmmd 1 64 16 17 49 48 32 33 pkg-004396 figure 139. 64-lead lead frame chip scale package [lfcsp] 9 mm 9 mm body and 0.75 mm package height (cp-64-15) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad7771bcpz ?40c to +125c 64-lead lead frame chip scale package [lfcsp] cp-64-15 ad7771bcpz-rl ?40c to +125c 64-lead lead frame chip scale package [lfcsp] cp-64-15 eval-ad7771fmcz evaluation board 1 z = rohs compliant part. ?2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d13802-0-6/17(0)

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